firtool-1.134.0

What's Changed

• [circt-verilog-lsp] Move to Slang's src mngr, drop LLVM src mngr by @Scheremo in #9045
• [circt-verilog-lsp][NFC] Break out implementation classes by @Scheremo in #9051
• [circt-verilog-lsp] Avoid recursing into other buffers when indexing by @Scheremo in #9055
• [RTG] Implement getAsmResultNames for FixedRegisterOp by @maerhart in #9058
• [CombToDatapath] Lower comb::SubOp by @uenoku in #9053
• [circt-synth] Allow AIGER file to be an input file by @uenoku in #9054
• [ESI] ChannelMMIO: decrease MMIO space per client by @teqdruid in #9062
• [RTG][EmbedValidationValuesPass] Allow ID duplicates if values match by @maerhart in #9061
• [RTG] Add isa.space operation by @maerhart in #9060
• [circt-verilog-lsp] Refactor VerilogIndex, add Package indexing by @Scheremo in #9065
• [CombToSynth] Compute Kogge-Stone prefix tree lazily in unsigned comparison lowering by @uenoku in #9050
• [ESI] Various tweaks to cosim scripts by @mortbopet in #9064
• [ESI][Runtime] Search for backends via env var by @teqdruid in #9070
• [RTG] Add VirtualRegisterConfigAttr by @maerhart in #9059
• [Comb] Fix mux canonicalizers for non-signless-ints by @teqdruid in #9071
• [circt-verilog-lsp] Minimize project-scope File IO by @Scheremo in #9056
• [circt-lsp-verilog] "Debounce" onDidChange calls; update in worker by @Scheremo in #9046
• [circt-lsp-server] Only enable unit tests if feature is enabled by @rwy7 in #9072
• [python][Synth] Provide fine-grained APIs for path queries by @uenoku in #9068
• [ImportVerilog][MooreToCore] Implement CHandle import and lowering by @Scheremo in #9077
• [ImportVerilog][MooreToCore] Re-land Implement CHandle import and low… by @Scheremo in #9079
• [FIRRTL] Add LowerDomains pass by @seldridge in #8929
• [MooreToCore] Support slicing of nested arrays by @SimonEbner in #9073
• [LLHD] Remove unused passes and unused memory types and ops by @fabianschuiki in #9078
• [circt-verilog-lsp-server] Simplify MaxCapForcesFlushDuringContinuousTyping by removing bakground thread by @uenoku in #9080
• [LLHD] Add new RefType to replace hw::InOutType by @fabianschuiki in #9081
• Fix minor typos by @SimonEbner in #9084
• [circt-lsp-server] Make time source injectable by @Scheremo in #9082
• [ImportVerilog] Add delayed assignment support by @fabianschuiki in #9085
• Revert "[circt-lsp-server] Make time source injectable" by @Scheremo in #9089
• [ImportVerilog][Moore] Add real-to-int & int-to-real operators by @Scheremo in #9088
• [FIRRTL] Add fields to domains by @seldridge in #9087
• [Synth] Enhance LowerVariadic pass with timing-aware optimization by @uenoku in #9086
• [Synth] Add MaximumAndCover Pass by @uenoku in #9090
• [ImportVerilog] Generalize materialization of constant real values by @Scheremo in #9092
• Bump LLVM to 3c53adec68b3e7be3d69bc4e24168e530097fce0. by @mikeurbach in #9063
• [FIRRTL] Add DomainDefineOp by @rwy7 in #9067
• [FIRRTL] DomainFieldAttr types are PropertyTypes by @seldridge in #9094
• Bump Slang to v9.1 by @fabianschuiki in #9097
• [FIRRTL] Update port insertion/erasure API for instance/instance-choice ops by @rwy7 in #9093
• [Synth][LowerVariaidc] Fix topological ordering and a pass phase ordering by @uenoku in #9095
• [ESI] Add opt-out of reversal in array C++ ser/de by @mortbopet in #9096
• [FIRRTL] Add LowerDomains to firtool pipeline by @seldridge in #9099
• [MooreToCore] Lower moore.real_constant to arith.constant by @Scheremo in #9100
• [FIRRTL] Fix dedup looking up wrong op in inner ref target check by @fabianschuiki in #9104
• [ImportVerilog] Allow functions to capture values from parent scope by @Scheremo in #9107
• [Synth] Fix race condition and memory corruption in longest path analysis caching by @uenoku in #9098

New Contributors

• @SimonEbner made their first contribution in #9073

Full Changelog: firtool-1.133.0...firtool-1.134.0