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The circt-verilog pipeline uses only a subset of the passes in the LLHD dialect. A few of the passes have been superseded by a reworked version which currently coexists with the original pass. Remove the old passes.

We also don't use the LLHD PtrType and the related operations anywhere in CIRCT. It looks like SV and VHDL are going to be easier to model if we treat everything as a signal, but have blocking assignments to model the behavior of variables. Remove these ops and the pointer type.

The circt-verilog pipeline uses only a subset of the passes in the LLHD
dialect. A few of the passes have been superseded by a reworked version
which currently coexists with the original pass. Remove the old passes.

We also don't use the LLHD `PtrType` and the related operations anywhere
in CIRCT. It looks like SV and VHDL are going to be easier to model if
we treat everything as a signal, but have blocking assignments to model
the behavior of variables. Remove these ops and the pointer type.
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LGTM. Just one mega nit:
The block diagram docs/dialects.drawio still refers to Desequentialization in arrow 8.
Otherwise the removal seems quite thorough to me.

@fabianschuiki
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Good point! I guess we still have the Deseq pass, but it might make sense to adjust the name in the diagram to match that!

@fabianschuiki fabianschuiki merged commit 0dd8d0d into main Oct 10, 2025
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@fabianschuiki fabianschuiki deleted the fschuiki/llhd-dce branch October 10, 2025 20:12
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3 participants