[ImportVerilog][MooreToCore] Re-land Implement CHandle import and low… #9079
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…ering Re-lands llvm#9077 which was reverted because it was unsquashed. Add end-to-end support for SystemVerilog `chandle`: - Import from Slang as `moore.chandle`. - Lower to `!llvm.ptr` in MooreToCore. - Treat `ref<chandle>` as a *by-ref SSA* value (no `hw.inout`). - Default-initialize to `llvm.mlir.zero : !llvm.ptr`.
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Re-lands #9077 which was reverted because it was unsquashed.
Add end-to-end support for SystemVerilog
chandle:moore.chandle.!llvm.ptrin MooreToCore.ref<chandle>as a by-ref SSA value (nohw.inout).llvm.mlir.zero : !llvm.ptr.