SystemVerilog and moving to logic #59
stevejAnnotations
1 error
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gl_test
Process completed with exit code 1.
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Artifacts
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GDS_logs
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10.2 MB |
sha256:c8483ff8ce822f0a6db8ef572c9f0b3cad25b32a83f427cd58600eb1b08cf94a
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gatelevel_test_vcd
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22.3 KB |
sha256:1e302a7e6274e95cfa6bb5c41851fa4a97e728cbcac7fde2f8bb3d651bed4396
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gds_render
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184 KB |
sha256:5c40a75647effa589806a220b68a1f266271090332c7571049e3cb91f9584c8e
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github-pages
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1.07 MB |
sha256:4f9c5e979a57d219a148e05ae20fdac15e3bd4d724b986a7b13a0564aa44cba7
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precheck_reports
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6.13 KB |
sha256:eb24ca9c6ed375b757ff6afad21af3ae9ef860530cf709c07ac55e451a4f2050
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tt_submission
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344 KB |
sha256:5a4ea0acb4bef545aab83142c039090ffe6fa3ac15f5081827d451137530f027
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