SystemVerilog and moving to logic

Author: stevej

info.yaml

@@ -4,7 +4,7 @@ project:
   author:       "Steve Jenson <[email protected]>"      # Your name
   discord:      "shorts_weather"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
   description:  "An example implementation the JTAG TAP state machine and basic boundary scan."      # One line description of what your project does
-  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
+  language:     "SystemVerilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
   clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.

src/byte_transmitter.v

@@ -8,13 +8,13 @@
 module byte_transmitter (
 `ifdef FORMAL (*gclk*)
 `endif
-    input wire clk_tck,
-    input wire reset,
-    input wire enable,
+    input logic clk_tck,
+    input logic reset,
+    input logic enable,
     // TODO: make size configurable
-    input wire [31:0] in,  // byte_buffer
-    output wire out,
-    output wire done
+    input logic [31:0] in,  // byte_buffer
+    output logic out,
+    output logic done
 );
 
 `ifdef FORMAL