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stevej / tt09-jtag-example-v2-stevej Public

generated from TinyTapeout/tt09-verilog-template

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gds

SystemVerilog and moving to logic #59

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SystemVerilog and moving to logic

SystemVerilog and moving to logic #59

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Summary
Jobs
- gds
- precheck
- gl_test
- viewer
Run details
- Usage
- Workflow file

Usage Workflow file

Annotations

1 error

Process completed with exit code 1.

The logs for this run have expired and are no longer available.

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