Verilog: generate property description prior to expression synthesis #585
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kroening
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tautschnig
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Jul 10, 2024
src/verilog/expr2verilog.cpp
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| const hierarchical_identifier_exprt &src, | ||
| unsigned &precedence) | ||
| { | ||
| precedence = 22; |
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Could you please add a comment for this magic number?
src/verilog/expr2verilog.cpp
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| to_verilog_indexed_part_select_plus_or_minus_expr(src), precedence = 18); | ||
| } | ||
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| else if(src.id() == ID_verilog_non_indexed_part_select) | ||
| return convert_non_indexed_part_select( | ||
| to_verilog_non_indexed_part_select_expr(src), precedence = 18); |
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Could you please add comments for those magic numbers?
tautschnig
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Jul 10, 2024
| @@ -1,7 +1,7 @@ | |||
| CORE | |||
| named_property1.sv | |||
| --bound 0 | |||
| ^\[main\.assert\.1\] always main\.x == 10: PROVED up to bound 0$ | |||
| ^\[main\.assert\.1\] always main\.x_is_ten: PROVED up to bound 0$ | |||
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I would have expected x_is_ten to make it into the property identifier, but maybe that's a misconception on my part?
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Ah, no, there is a some terminology issue here: The identifier is for assertions, not Verilog properties. Verilog properties may or may not end up as an assertion, assumption, cover statement, etc.
Verilog properties do not get checked by default.
This generates the property description from the expression prior to synthsis, which is closer to the Verilog source code.
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This generates the property description from the expression prior to synthesis, which is closer to the Verilog source code.