SystemVerilog: named properties #579
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Concurrent assertion items (assert/assume/cover) that are module items with a block label go into the module name space, not into a separate "property" name space. Assertion items without block item now get a label based on the kind of the assertion item (assert/assume/cover).
kroening
force-pushed
the
named_property1
branch
2 times, most recently
from
a613ace to
f7c6ec7
Compare
This adds support for SystemVerilog named properties.
kroening
force-pushed
the
named_property1
branch
from
f7c6ec7 to
94604a9
Compare
tautschnig
reviewed
Jun 25, 2024
| CORE | ||
| named_property1.sv | ||
| --bound 0 | ||
| ^\[main\.assert\.1\] always main\.x == 10: PROVED up to bound 0$ |
There was a problem hiding this comment.
Wouldn't it make sense for x_is_ten to be used here in some way?
There was a problem hiding this comment.
I'd like that -- it would require splitting up the type checking phase such that the initial phase doesn't expand symbols marked as "macro". Will do eventually.
tautschnig
approved these changes
Jun 28, 2024
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This adds support for SystemVerilog named properties.