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[vlsi][ci skip] Fix tutorial.mk so that INPUT_CONFS override only affects tutorials #1631

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Merged
jerryz123 merged 1 commit into from
Oct 19, 2023
Merged

[vlsi][ci skip] Fix tutorial.mk so that INPUT_CONFS override only affects tutorials #1631

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4 changes: 3 additions & 1 deletion vlsi/tutorial.mk
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Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,7 @@ ifeq ($(tutorial),asap7)
TECH_CONF ?= example-asap7.yml
DESIGN_CONFS ?=
VLSI_OBJ_DIR ?= build-asap7-commercial
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
endif

ifeq ($(tutorial),sky130-commercial)
Expand All @@ -23,6 +24,7 @@ ifeq ($(tutorial),sky130-commercial)
$(if $(filter $(VLSI_TOP),Rocket), \
example-designs/sky130-rocket.yml, )
VLSI_OBJ_DIR ?= build-sky130-commercial
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
endif

ifeq ($(tutorial),sky130-openroad)
Expand All @@ -36,8 +38,8 @@ ifeq ($(tutorial),sky130-openroad)
$(if $(filter $(VLSI_TOP),RocketTile), \
example-designs/sky130-openroad-rockettile.yml, )
VLSI_OBJ_DIR ?= build-sky130-openroad
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
# Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time.
ENABLE_YOSYS_FLOW = 1
endif

INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)