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don't start at 0, make enough room for states docs #61: Commit 86a5fcd pushed by stevej
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fpga workflow isn't important, I guess docs #60: Commit 697c4b9 pushed by stevej
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SystemVerilog and moving to logic docs #59: Commit ffb1bde pushed by stevej
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moving to always_ff docs #58: Commit f52449f pushed by stevej
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run fpga workflow on each push docs #57: Commit 5d0d22e pushed by stevej
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added harden.log to .gitignore docs #56: Commit 83d7021 pushed by stevej
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remove dead code, formatting and new comment docs #55: Commit 50ce1ee pushed by stevej
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more SystemVerilog changes and style change for clk docs #54: Commit 7d1fb92 pushed by stevej
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beginning the full shift to SystemVerilog: change fpga Makefile, use … docs #53: Commit f0e72f1 pushed by stevej
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use gclk only for formal tests, add it to the bmc options docs #52: Commit dcb2296 pushed by stevej
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add nettypes, remove been_reset, add better comment docs #51: Commit 2626d77 pushed by stevej
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formal method to ensure we can leave the TAP FSM docs #50: Commit b28431c pushed by stevej
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Merge branch 'main' of github.com:stevej/tt09-jtag-example-v2-stevej docs #49: Commit 4d8c202 pushed by stevej
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Update README.md docs #48: Commit 8400e1a pushed by stevej
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add debug bits to see how far we're getting in the TAP state machine … docs #47: Commit 9156866 pushed by stevej
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tell yosys that clk is the global clock docs #46: Commit 5086ef0 pushed by stevej
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write to TDO on the negative edge. This adds a half-cycle delay to av… docs #45: Commit 4e0398f pushed by stevej
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TRST being high too early breaks GL simulation docs #44: Commit ef61f98 pushed by stevej
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explicit widths, switch to one-hot encoding for the TAP state machine docs #43: Commit e317398 pushed by stevej
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start with TRST and TCK high then low docs #42: Commit e4bbaa9 pushed by stevej
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fix a fencepost error by setting byte_transmitter_enable high a clock… docs #41: Commit 6ed3c7f pushed by stevej
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remove mux for simplicity, shuffle some bits around docs #40: Commit e93a080 pushed by stevej
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fixing current_state to be the right number of bits, fixing an assert… docs #39: Commit 8840286 pushed by stevej
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tighten up formal tests docs #38: Commit 0e56230 pushed by stevej
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stripping minipit down to basics docs #37: Commit f5ea9bf pushed by stevej
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