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SystemVerilog and moving to logic #59

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SystemVerilog and moving to logic

SystemVerilog and moving to logic #59

Triggered via push November 6, 2024 20:24
@stevejstevej
pushed ffb1bde
main
Status Success
Total duration 32s
Artifacts 1

test.yaml

on: push
test
23s
test
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test-vcd Expired
2.87 KB
sha256:e487ca1837c4c3273c1888c3b5674a2b7d74ed3656fd11c65e75d7786e776ff5