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@uenoku uenoku commented Dec 3, 2025

This option controls whether assignments are emitted separately from declarations or inlined within them. When enabled, both continuous assignments and blocking assignments are always emitted separately rather than being inlined in net and variable declarations.

This is useful for tools or coding styles that prefer explicit separation between declarations and assignments, improving compatibility with certain linters or synthesis tools.

Fixes #9297.

This option controls whether assignments are emitted separately from
declarations or inlined within them. When enabled, both continuous
assignments and blocking assignments are always emitted separately
rather than being inlined in net and variable declarations.

This is useful for tools or coding styles that prefer explicit
separation between declarations and assignments, improving
and compatibility with certain linters or synthesis tools.
@uenoku uenoku requested review from darthscsi and seldridge December 3, 2025 21:07
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LGTM

Comment on lines 4 to 21
// CHECK-LABEL: module test(
// DISALLOW-LABEL: module test(
hw.module @test(in %v: i1) {
// CHECK: wire w = v;
// DISALLOW: wire w;
// DISALLOW: assign w = v;
%w = sv.wire : !hw.inout<i1>
sv.assign %w, %v : i1
// CHECK: initial begin
// DISALLOW: initial begin
sv.initial {
// CHECK: automatic logic l = v;
// DISALLOW: automatic logic l;
// DISALLOW-NEXT: l = v;
%l = sv.logic : !hw.inout<i1>
sv.bpassign %l, %v : i1
}
}
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Nit: you can collapse a lot of the checks down using --check-prefixes=CHECK,ALLOW and --check-prefixes=CHECK,DISALLOW to avoid some of the FileCheck duplication.

Comment on lines +16 to +17
// DISALLOW: automatic logic l;
// DISALLOW-NEXT: l = v;
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It is outside of my understanding of the spec to know if this makes sense. You may want to throw this at verilator --lint-only and make sure it's happy with it. I realize we generally avoid any use of automatic logic due to old problems with tools.

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Verilator is ok with this (and we've emitted this form when it's not possible to inline the assignment). automatic logic for sure has poor support generally so I feel we should flip the option at this point.

@uenoku uenoku merged commit 9ace595 into llvm:main Dec 3, 2025
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[ExportVerilog] Add a loweringOption to disallow expressions in declarations

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