[ExportVerilog] Add a loweringOption to disallow expressions in declarations

[seldridge]

Consider the following input FIRRTL circuit:

FIRRTL version 5.1.0
circuit Foo: %[[
  {
    "class": "firrtl.transforms.DontTouchAnnotation",
    "target": "~|Foo>c"
  }
]]

  public module Foo:
    input a: UInt<1>
    input b: UInt<1>

    node c = and(a, b)

Currently, this will compile to the following (firtool Foo.fir):

// Generated by CIRCT firtool-1.137.0-51-g0816b653d
module Foo(
  input a,
        b
);

  wire c = a & b;
endmodule

Add a lowering option which can compile this to:

// Generated by CIRCT firtool-1.137.0-51-g0816b653d
module Foo(
  input a,
        b
);

  wire c;
  assign c = a & b;
endmodule