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[SeqToSV] Use XMR to set up async reset and preset of firreg under ifdef #8944

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Merged
rwy7 merged 2 commits into from
Sep 12, 2025
Merged

[SeqToSV] Use XMR to set up async reset and preset of firreg under ifdef #8944

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9610c92
[SeqToSV] Use XMR to set up async reset of firreg
rwy7 Sep 11, 2025
999e48d
[SeqToSV] Initialize buried preset registers using XMRs
rwy7 Sep 11, 2025
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39 changes: 28 additions & 11 deletions lib/Conversion/SeqToSV/FirRegLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,13 @@ using llvm::MapVector;

#define DEBUG_TYPE "lower-seq-firreg"

static Value buildXMRTo(OpBuilder &builder, HierPathOp path, Location loc,
Type type) {
auto name = path.getSymNameAttr();
auto ref = mlir::FlatSymbolRefAttr::get(name);
return sv::XMRRefOp::create(builder, loc, type, ref);
}

/// Immediately before the terminator, if present. Otherwise, the block's end.
static Block::iterator getBlockEnd(Block *block) {
if (block->mightHaveTerminator())
Expand Down Expand Up @@ -350,6 +357,8 @@ void FirRegLowering::createRandomInitialization(ImplicitLocOpBuilder &builder) {

void FirRegLowering::createPresetInitialization(ImplicitLocOpBuilder &builder) {
for (auto &svReg : presetInitRegs) {
OpBuilder::InsertionGuard guard(builder);

auto loc = svReg.reg.getLoc();
auto elemTy = svReg.reg.getType().getElementType();
auto cst = getOrCreateConstant(loc, svReg.preset.getValue());
Expand All @@ -360,7 +369,13 @@ void FirRegLowering::createPresetInitialization(ImplicitLocOpBuilder &builder) {
else
rhs = hw::BitcastOp::create(builder, loc, elemTy, cst);

sv::BPAssignOp::create(builder, loc, svReg.reg, rhs);
buildRegConditions(builder, svReg.reg);
Value target = svReg.reg;
if (svReg.path)
target = buildXMRTo(builder, svReg.path, svReg.reg.getLoc(),
svReg.reg.getType());

sv::BPAssignOp::create(builder, loc, target, rhs);
}
}

Expand All @@ -370,13 +385,22 @@ void FirRegLowering::createPresetInitialization(ImplicitLocOpBuilder &builder) {
void FirRegLowering::createAsyncResetInitialization(
ImplicitLocOpBuilder &builder) {
for (auto &reset : asyncResets) {
OpBuilder::InsertionGuard guard(builder);

// if (reset) begin
// ..
// end
sv::IfOp::create(builder, reset.first, [&] {
for (auto &reg : reset.second)
sv::BPAssignOp::create(builder, reg.reg.getLoc(), reg.reg,
sv::IfOp::create(builder, reset.first, [&]() {
for (auto &reg : reset.second) {
OpBuilder::InsertionGuard guard(builder);
buildRegConditions(builder, reg.reg);
Value target = reg.reg;
if (reg.path)
target = buildXMRTo(builder, reg.path, reg.reg.getLoc(),
reg.reg.getType());
sv::BPAssignOp::create(builder, reg.reg.getLoc(), target,
reg.asyncResetValue);
}
});
}
}
Expand Down Expand Up @@ -798,13 +822,6 @@ void FirRegLowering::buildRegConditions(OpBuilder &b, sv::RegOp reg) {
}
}

static Value buildXMRTo(OpBuilder &builder, HierPathOp path, Location loc,
Type type) {
auto name = path.getSymNameAttr();
auto ref = mlir::FlatSymbolRefAttr::get(name);
return sv::XMRRefOp::create(builder, loc, type, ref);
}

void FirRegLowering::initialize(OpBuilder &builder, RegLowerInfo reg,
ArrayRef<Value> rands) {
auto loc = reg.reg.getLoc();
Expand Down
58 changes: 58 additions & 0 deletions test/Dialect/Seq/firreg.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -1011,3 +1011,61 @@ hw.module @RegUnderIfdefDupName(in %clock : !seq.clock, in %reset : i1, in %valu
}
hw.output
}

// Test for registers with async resets.

// CHECK: hw.hierpath @[[reg_path:.+]] [@AsyncResetRegUnderIfdef::@reg]
hw.module @AsyncResetRegUnderIfdef(in %clock : !seq.clock, in %reset : i1, in %value : i1) {
%c = hw.constant 0 : i1

// CHECK: sv.ifdef @MyMacro {
// CHECK: %reg = sv.reg sym @reg : !hw.inout<i1>
// CHECK: %0 = sv.read_inout %reg : !hw.inout<i1>
// CHECK: sv.always posedge %clock, posedge %reset {
// CHECK: sv.if %reset {
// CHECK: sv.passign %reg, %false_0 : i1
// CHECK: } else {
// CHECK: sv.passign %reg, %value : i1
// CHECK: }
// CHECK: }
// CHECK: }
sv.ifdef @MyMacro {
%reg = seq.firreg %value clock %clock reset async %reset, %c : i1
}

// CHECK: sv.initial {
// CHECK: sv.if %reset {
// CHECK: sv.ifdef.procedural @MyMacro {
// CHECK: %0 = sv.xmr.ref @[[reg_path]] : !hw.inout<i1>
// CHECK: sv.bpassign %0, %false_0 : i1
// CHECK: }
// CHECK: }
// CHECK: }
hw.output
}

// Test for registers with "preset".

// CHECK: hw.hierpath @[[reg_path:.+]] [@PresetRegUnderIfdef::@reg]
hw.module @PresetRegUnderIfdef(in %clock : !seq.clock, in %value : i1) {
%c = hw.constant 0 : i1

// CHECK: sv.ifdef @MyMacro {
// CHECK: %reg = sv.reg sym @reg : !hw.inout<i1>
// CHECK: %0 = sv.read_inout %reg : !hw.inout<i1>
// CHECK: sv.always posedge %clock {
// CHECK: sv.passign %reg, %value : i1
// CHECK: }
// CHECK: }
sv.ifdef @MyMacro {
%reg = seq.firreg %value clock %clock preset 0: i1
}

// CHECK: sv.initial {
// CHECK: sv.ifdef.procedural @MyMacro {
// CHECK: %0 = sv.xmr.ref @[[reg_path]] : !hw.inout<i1>
// CHECK: sv.bpassign %0, %false : i1
// CHECK: }
// CHECK: }
hw.output
}