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@rwy7 rwy7 commented Sep 11, 2025

With inline layers, firregs may now appear under ifdef blocks. This PR updates the generation of the reset IR to reference a firreg by XMR if the register is buried under an ifdef.

@rwy7 rwy7 added FIRRTL Involving the `firrtl` dialect Seq Involving the `seq` dialect SV System Verilog Dialect labels Sep 11, 2025
@rwy7 rwy7 linked an issue Sep 11, 2025 that may be closed by this pull request
@rwy7 rwy7 force-pushed the fix-async-reg-reset-under-ifdef branch 2 times, most recently from f477454 to 3ff7ba5 Compare September 11, 2025 14:11
@rwy7 rwy7 changed the title [SeqToSV] Use XMR to set up async reset of firreg [SeqToSV] Use XMR to set up async reset and preset of firreg under ifdef Sep 11, 2025
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rwy7 commented Sep 11, 2025

Updated to also fix the same issue for preset registers.

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This looks great. Thank you for quickly getting this fixed!

I am also glad that all the infra was almost there to do this. 😌

sv::BPAssignOp::create(builder, reg.reg.getLoc(), target,
reg.asyncResetValue);
}
builder.setInsertionPointAfter(ifOp);
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Same as above. Consider InsertionGuard. Suggestion only, non-blocking.

@rwy7 rwy7 force-pushed the fix-async-reg-reset-under-ifdef branch 3 times, most recently from d77c1ed to 55a8c2e Compare September 11, 2025 19:06
With inline layers, firregs may now appear under ifdef blocks. This PR
updates the generation of the reset IR to reference a firreg by XMR if
the register is buried under an ifdef.
@rwy7 rwy7 force-pushed the fix-async-reg-reset-under-ifdef branch from 55a8c2e to 999e48d Compare September 12, 2025 02:15
@rwy7 rwy7 merged commit a71e160 into llvm:main Sep 12, 2025
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@rwy7 rwy7 deleted the fix-async-reg-reset-under-ifdef branch September 12, 2025 14:09
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FIRRTL Involving the `firrtl` dialect Seq Involving the `seq` dialect SV System Verilog Dialect

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[Seq] LowerSeqToSV Creating Illegal IR

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