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Verilog: allow top-level package items #287

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Merged
merged 1 commit into from
Dec 12, 2023
Merged

Verilog: allow top-level package items #287

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29 changes: 14 additions & 15 deletions src/verilog/parser.y
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Original file line number Diff line number Diff line change
Expand Up @@ -616,16 +616,11 @@ description:
| interface_declaration
| program_declaration
| package_declaration
| attribute_instance_brace package_item
| attribute_instance_brace bind_directive
| config_declaration
| type_declaration
{ PARSER.parse_tree.create_typedef(stack_expr($1)); }
;

/*
| attribute_instance_brace package_item
*/

module_nonansi_header:
attribute_instance_brace
module_keyword
Expand Down Expand Up @@ -842,6 +837,19 @@ bind_directive:
// A.1.11 Package items

package_item:
package_or_generate_item_declaration
// | anonymous_program
// | package_export_declaration
// | timeunits_declaration
;

package_or_generate_item_declaration:
net_declaration
| data_declaration
| task_declaration
| function_declaration
| local_parameter_declaration ';'
| parameter_declaration ';'
;

// System Verilog standard 1800-2017
Expand Down Expand Up @@ -1958,15 +1966,6 @@ generate_item_or_null:

constant_expression: expression;

package_or_generate_item_declaration:
net_declaration
| data_declaration
| task_declaration
| function_declaration
| local_parameter_declaration ';'
| parameter_declaration ';'
;

// System Verilog standard 1800-2017
// A.5.1 UDP declaration

Expand Down