Verilog: allow top-level package items #287
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tautschnig
approved these changes
Dec 11, 2023
src/verilog/parser.y
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| @@ -616,16 +616,13 @@ description: | |||
| | interface_declaration | |||
| | program_declaration | |||
| | package_declaration | |||
| // | type_declaration | |||
| // { PARSER.parse_tree.create_typedef(stack_expr($1)); } | |||
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Here and below: could a comment please be added to clarify why these are commented out?
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I should drop that rule altogether; it's subsumed by the newly added rules.
This adds the System Verilog grammar rules to allow top-level package items.
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This adds the System Verilog grammar rules to allow top-level package items.