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Uset systemRDL to generate UVM regmodel or Verilog C use header files

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Name		Name	Last commit message	Last commit date
Latest commit History 45 Commits
ralbot		ralbot
test		test
README.md		README.md
ralbotgen.py		ralbotgen.py
rdlcompiler.py		rdlcompiler.py
setup.py		setup.py

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Generate uvm regmodel and C header file

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Uset systemRDL to generate UVM regmodel or Verilog C use header files

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