ucb-bar · jerryz123 · Aug 12, 2024 · Aug 11, 2024
diff --git a/README.md b/README.md
@@ -16,7 +16,7 @@ To get started using Chipyard, see the documentation on the Chipyard documentati
 
 Chipyard is an open source framework for agile development of Chisel-based systems-on-chip.
 It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators.
-Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6 (Ariane)][cva6]), vector units ([Saturn](https://github.com/ucb-bar/saturn-vectors), [Ara](https://github.com/pulp-platform/ara)), accelerators ([Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
+Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6 (Ariane)][cva6]), vector units ([Saturn](saturn), [Ara](ara)), accelerators ([Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
 Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]).
 Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley].
 
@@ -98,3 +98,5 @@ This work is supported by the NSF CCRI ENS Chipyard Award #2016662.
 [cva6]: https://github.com/openhwgroup/cva6/
 [gemmini]: https://github.com/ucb-bar/gemmini
 [nvdla]: http://nvdla.org/
+[saturn]: https://github.com/ucb-bar/saturn-vectors
+[ara]: https://github.com/pulp-platform/ara
diff --git a/docs/Generators/Saturn.rst b/docs/Generators/Saturn.rst
@@ -7,13 +7,14 @@ Saturn implements a compact short-vector-length vector microarchitecture suitabl
 More documentation on Saturn will be released in the future.
 A partial listing of supported Saturn configurations is in ``generators/chipyard/src/main/scala/config/SaturnConfigs.scala``.
 
- * Full support for `V` application-profile RVV 1.0
+ * Full support for ``V`` application-profile RVV 1.0
  * Precise traps with virtual memory
  * Indexed/strided/segmented loads and stores
  * Mask operations
  * Register-gather + reductions
- * `Zvfh` support for vector half-precision floating-point (FP16)
- * `Zve64d` support for vector FP32 and FP64
- * Configurable vector length, from `Zvl64b` up (tested to `Zvl4096b`)
+ * ``Zvfh`` support for vector half-precision floating-point (FP16)
+ * ``Zvbb`` support for vector basic bit-manipulation instructions
+ * ``Zve64d`` support for vector FP32 and FP64
+ * Configurable vector length, from ``Zvl64b`` up (tested to ``Zvl4096b``)
  * Configurable datapath width, from 64b up (tested to 512b)
 
diff --git a/generators/ara b/generators/ara
diff --git a/generators/rocket-chip b/generators/rocket-chip
diff --git a/generators/saturn b/generators/saturn
diff --git a/generators/shuttle b/generators/shuttle
+1 −0		src/main/scala/rocket/RocketCore.scala
+2 −1		src/main/scala/rocket/VectorUnit.scala
+1 −1		src/main/scala/tile/BaseTile.scala
+1 −0		src/main/scala/tile/Core.scala
+29 −0		LICENSE
+8 −1		README.md
+5,634 −1,026		benchmarks/vec-exp/data.S
+2 −1		benchmarks/vec-exp/main.c
+72 −34		benchmarks/vec-fconv2d/fconv2d_7x7.c
+9 −0		benchmarks/vec-fconv2d/main.c
+0 −6		benchmarks/vec-fconv3d/fconv3d.h
+15 −404		benchmarks/vec-fconv3d/fconv3d_3x7x7.c
+7 −0		benchmarks/vec-fconv3d/main.c
+10 −0		benchmarks/vec-fft/fft2_main.c
+24 −476		benchmarks/vec-jacobi2d/jacobi2d.c
+5 −1		benchmarks/vec-jacobi2d/main.c
+2,274 −1,518		benchmarks/vec-sgemm-v3/dataset1.h
+3 −2		benchmarks/vec-sgemm-v3/vec-sgemm_main.c
+5 −0		benchmarks/vec-spmv/main.c
+68 −13		src/main/scala/backend/Backend.scala
+7 −6		src/main/scala/backend/ExecuteSequencer.scala
+3 −2		src/main/scala/backend/LoadSequencer.scala
+8 −2		src/main/scala/backend/PermuteSequencer.scala
+4 −2		src/main/scala/backend/PipeSequencer.scala
+54 −29		src/main/scala/backend/RegisterFile.scala
+2 −1		src/main/scala/backend/StoreSequencer.scala
+3 −3		src/main/scala/common/Bundles.scala
+4 −2		src/main/scala/common/Consts.scala
+26 −26		src/main/scala/common/Parameters.scala
+0 −9		src/main/scala/exu/ExecutionUnit.scala
+0 −3		src/main/scala/exu/FunctionalUnit.scala
+0 −1		src/main/scala/exu/fp/ElementwiseFPU.scala
+174 −430		src/main/scala/exu/fp/FPDiv.scala
+0 −1		src/main/scala/exu/fp/SharedFPMisc.scala
+3 −1		src/main/scala/exu/int/BitwisePipe.scala
+0 −1		src/main/scala/exu/int/IntegerDivide.scala
+61 −13		src/main/scala/exu/int/IntegerPipe.scala
+33 −9		src/main/scala/exu/int/ShiftPipe.scala
+6 −5		src/main/scala/frontend/Dispatch.scala
+2 −1		src/main/scala/frontend/EarlyDecode.scala
+13 −3		src/main/scala/frontend/EarlyTrapCheck.scala
+12 −4		src/main/scala/frontend/HwachaLimiter.scala
+3 −2		src/main/scala/insns/Control.scala
+0 −1		src/main/scala/insns/Decode.scala
+22 −7		src/main/scala/insns/Instructions.scala
+6 −4		src/main/scala/mem/Mem.scala
+1 −1		src/main/scala/mem/StoreSegmenter.scala
+3 −1		src/main/scala/rocket/Configs.scala
+3 −1		src/main/scala/shuttle/Configs.scala