Add reset pipeline support

[jerryz123]

This adds support for pipelining the synchronized reset to downstream digital blocks, improving PD for large SoCs which need pipelined reset to physically distant sinks. Note that this relies partially on syn/par tools being able to perform register duplication to improve timing.

Verilator doesn't like this since this leads to a pre-reset phase as the pipeline drains into the downstream components.

Related PRs / Issues:

Type of change:

• Bug fix
• New feature
• Other enhancement

Impact:

• RTL change
• Software change (RISC-V software)
• Build system change
• Other

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