EXT_FILELISTS and EXT_INCDIR APIs for including external verilog projects

[jerryz123]

External projects which may not want to provide their sources as a blackbox resource, can instead append to these Makefile variables.

Related PRs / Issues:

Type of change:

• Bug fix
• New feature
• Other enhancement

Impact:

• RTL change
• Software change (RISC-V software)
• Build system change
• Other

Contributor Checklist:

• Did you set main as the base branch?
• Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
• Did you state the type-of-change/impact?
• Did you delete any extraneous prints/debugging code?
• Did you mark the PR with a changelog: label?
• (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file?
• (If applicable) Did you add documentation for the feature?
• (If applicable) Did you add a test demonstrating the PR?

• (If applicable) Did you mark the PR as Please Backport?

[joonho3020]

SFTM

[jerryz123]

FWIW I'm in favor of merging this now. I will soon upstream project integration which demonstrates this feature

[harrisonliew]

Can you sync the VLSI Makefile with this? Would replace CUSTOM_VLOG.

[jerryz123]

Ah yes, that's a good idea, I'll do that

[harrisonliew]

Thanks. Section 5.10.2 of docs too.

[jerryz123]

Hmm its not quite the same though.. it looks like CUSTOM_VLOG lets you bypass the chipyard/chisel generators entirely,. How should we rectify this? I assume we want to keep the facility for runner hammer w/o the chisel generators?

[harrisonliew]

If I'm not understanding correctly, aren't you trying to bypass Chipyard/Chisel with this too, for doing simulations? Or are these files that you just append in addition to Chipyard-generated verilog? If it's the latter, then it needs to be appended to VLSI_RTL variable.

[jerryz123]

This doesn't bypass chipyard, it just appends additional source files. Adding to VLSI_RTL is correct I think

[abejgonzalez]

This LGTM. Two things to note:

• I think you can use this API to auto-generate filelists in elaboration by specifying a auto-gen.f that is populated in elaboration. This would be useful for projects like CVA6, NVDLA, IBEX, etc which different configurations of the Verilog incorporate different files.
• This isn't supported in FireSim right now (should be trivial to support).