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abejgonzalez
commented
Dec 13, 2023
| # Place SRAM memory instances | ||
| # SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag | ||
| # data cache | ||
| - path: "RocketTile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" |
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Do these paths need to change?
abejgonzalez
commented
Dec 13, 2023
| # Place SRAM memory instances | ||
| # SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag | ||
| # data cache | ||
| - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" |
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Do these paths need to change?
abejgonzalez
commented
Dec 14, 2023
Comment on lines
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| # Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time. | ||
| ENABLE_YOSYS_FLOW = 1 |
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This needs to get reverted.
harrisonliew
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Dec 15, 2023
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Though I opened the PR, I approve of this (now that @nayiri-k fixed things). Merging. |
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Now that CIRCT 1.60.0 is released it should support disabling packed arrays for Yosys.
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mainas the base branch?changelog:<topic>label?changelog:label?.conda-lock.ymlfile if you updated the conda requirements file?Please Backport?