Rebuild jars when sv/v files are changed + Add documentation on blackboxes

[abejgonzalez]

• Moves Verilog make dependencies up to jar generation so that Verilog files are properly updated in the jar. This was bugged before since you would have to recompile Scala sources to see the Verilog sources change.
• Adds documentation on some of the corner cases of adding blackboxes
• Updates insert includes script to be recursive (if an include has include within it, rerun the replacement)
• Bump firtool to 1.58.0
• Updates the generate-conda-lockfiles script to delete the lockfile before regenerating (fixes issue where conda-lock would get stuck regenerating the lockfile if the lockfile pre-existed)
• Moves GCD to avoid 0x1000 (same address as bootrom)

It also exposes a bug mentioned here: #1624 (comment). This is an issue in MFC that needs to get solved.

The error being that duplicate addPath calls cannot exist (not sure if having a different module name will fix the issue). Error message is the following:

Cannot find file /scratch/abejgonza/cy/generators/chipyard/src/main/resources/vsrc/GCDMMIOBlackBox.v

Related PRs / Issues:

Type of change:

• Bug fix
• New feature
• Other enhancement

Impact:

• RTL change
• Software change (RISC-V software)
• Build system change
• Other

Contributor Checklist:

• Did you set main as the base branch?
• Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
• Did you state the type-of-change/impact?
• Did you delete any extraneous prints/debugging code?
• Did you mark the PR with a changelog: label?
• (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file?
• (If applicable) Did you add documentation for the feature?
• (If applicable) Did you add a test demonstrating the PR?

• (If applicable) Did you mark the PR as Please Backport?

[abejgonzalez]

Testing with firtool-1.58 seems to fix the bug. I'll update the conda-forge feedstock.

[jerryz123]

LGTM.