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jerryz123 merged 2 commits into from
Mar 8, 2023
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Add graphml visualization section to docs #1387

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Add graphml visualization section
Mar 8, 2023
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Minor clarification in visualization section
Mar 8, 2023
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10 changes: 10 additions & 0 deletions docs/Simulation/Software-RTL-Simulation.rst
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Expand Up @@ -188,6 +188,16 @@ An open-source vcd-capable waveform viewer is `GTKWave <http://gtkwave.sourcefor
For a VCS simulation, this will generate a vpd file (this is a proprietary waveform representation format used by Synopsys) that can be loaded to vpd-supported waveform viewers.
If you have Synopsys licenses, we recommend using the DVE waveform viewer.

Visualizing Chipyard SoCs
--------------------------

During the creation of the simulation executable, a graphml file is emitted that will allow you to visualize your Chipyard SoC in a graph format.
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@abejgonzalez abejgonzalez Mar 8, 2023

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During the creation of Verilog, not just the simulation executable.

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@abejgonzalez abejgonzalez Mar 8, 2023

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Also, I would specify that this visualizes the diplomacy graph.

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@abejgonzalez abejgonzalez Mar 8, 2023

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Nit: graphml should be in ...


To view the graph, first download a viewer such as `yEd <https://www.yworks.com/products/yed/>`__.

The ``*.graphml`` file will be located in ``generated-src/<...>-<package>-<config>/``. Open the file in the graph viewer.
To get a clearer view of the SoC, switch to "hierarchical" view. For yEd, this would be done by selecting ``layout`` -> ``hierarchical``, and then choosing "Ok" without changing any settings.

.. _sw-sim-verilator-opts:

Additional Verilator Options
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