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jerryz123jerryz123
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Merge pull request #1476 from ucb-bar/serial-bump
Support uni-directional TLSerdesser
2 parents 76cf492 + f835390 commit 7184848

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11 files changed

+22
-49
lines changed

11 files changed

+22
-49
lines changed

‎.github/scripts/run-tests.sh‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -110,7 +110,8 @@ case $1 in
110110
make run-binary-fast -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/multiply.riscv
111111
;;
112112
chipyard-ibex)
113-
run_bmark ${mapping[$1]} #TODO: Find 32-bit test
113+
# Ibex cannot run the riscv-tests binaries for some reason
114+
# make run-binary-fast -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv32ui-p-simple
114115
;;
115116
chipyard-sodor)
116117
run_asm ${mapping[$1]}

‎generators/chipyard/src/main/scala/config/AbstractConfig.scala‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,7 @@ class AbstractConfig extends Config(
4747

4848
new testchipip.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address
4949
new testchipip.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address
50+
new testchipip.WithSerialTLClientIdBits(4) ++ // support up to 1 << 4 simultaneous requests from serialTL port
5051
new testchipip.WithSerialTLWidth(32) ++ // fatten the serialTL interface to improve testing performance
5152
new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM
5253
new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity

‎generators/chipyard/src/main/scala/config/ChipConfigs.scala‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,8 @@ class ChipLikeQuadRocketConfig extends Config(
2121
// Set up I/O
2222
//==================================
2323
new testchipip.WithSerialTLWidth(4) ++
24+
new testchipip.WithSerialTLBackingMemory ++ // Backing memory is over serial TL protocol
2425
new chipyard.harness.WithSimAXIMemOverSerialTL ++ // Attach fast SimDRAM to TestHarness
25-
new chipyard.config.WithSerialTLBackingMemory ++ // Backing memory is over serial TL protocol
2626
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ // 4GB max external memory
2727
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel
2828

‎generators/chipyard/src/main/scala/config/RocketConfigs.scala‎

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -13,9 +13,6 @@ class RocketConfig extends Config(
1313

1414
class TinyRocketConfig extends Config(
1515
new chipyard.iobinders.WithDontTouchIOBinders(false) ++ // TODO FIX: Don't dontTouch the ports
16-
new chipyard.config.WithTLSerialLocation(
17-
freechips.rocketchip.subsystem.FBUS,
18-
freechips.rocketchip.subsystem.PBUS) ++ // attach TL serial adapter to f/p busses
1916
new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology
2017
new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$
2118
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory
@@ -56,7 +53,6 @@ class GB1MemoryRocketConfig extends Config(
5653

5754
// DOC include start: l1scratchpadrocket
5855
class ScratchpadOnlyRocketConfig extends Config(
59-
new testchipip.WithSerialPBusMem ++
6056
new chipyard.config.WithL2TLBs(0) ++
6157
new freechips.rocketchip.subsystem.WithNBanks(0) ++
6258
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port
@@ -122,7 +118,7 @@ class MulticlockAXIOverSerialConfig extends Config(
122118
AsynchronousCrossing().sourceSync) ++
123119

124120
new chipyard.harness.WithSimAXIMemOverSerialTL ++ // add SimDRAM DRAM model for axi4 backing memory over the SerDes link, if axi4 mem is enabled
125-
new chipyard.config.WithSerialTLBackingMemory ++ // remove axi4 mem port in favor of SerialTL memory
121+
new testchipip.WithSerialTLBackingMemory ++ // remove axi4 mem port in favor of SerialTL memory
126122

127123
new freechips.rocketchip.subsystem.WithNBigCores(2) ++
128124
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel

‎generators/chipyard/src/main/scala/config/SodorConfigs.scala‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,6 @@ class Sodor1StageConfig extends Config(
88
// Create a Sodor 1-stage core
99
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++
1010
new testchipip.WithSerialTLWidth(32) ++
11-
new testchipip.WithSerialPBusMem ++
1211
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
1312
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
1413
new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -18,7 +17,6 @@ class Sodor2StageConfig extends Config(
1817
// Create a Sodor 2-stage core
1918
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++
2019
new testchipip.WithSerialTLWidth(32) ++
21-
new testchipip.WithSerialPBusMem ++
2220
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
2321
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
2422
new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -28,7 +26,6 @@ class Sodor3StageConfig extends Config(
2826
// Create a Sodor 1-stage core with two ports
2927
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++
3028
new testchipip.WithSerialTLWidth(32) ++
31-
new testchipip.WithSerialPBusMem ++
3229
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
3330
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
3431
new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -38,7 +35,6 @@ class Sodor3StageSinglePortConfig extends Config(
3835
// Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter)
3936
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++
4037
new testchipip.WithSerialTLWidth(32) ++
41-
new testchipip.WithSerialPBusMem ++
4238
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
4339
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
4440
new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -48,7 +44,6 @@ class Sodor5StageConfig extends Config(
4844
// Create a Sodor 5-stage core
4945
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++
5046
new testchipip.WithSerialTLWidth(32) ++
51-
new testchipip.WithSerialPBusMem ++
5247
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
5348
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
5449
new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -58,7 +53,6 @@ class SodorUCodeConfig extends Config(
5853
// Construct a Sodor microcode-based single-bus core
5954
new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++
6055
new testchipip.WithSerialTLWidth(32) ++
61-
new testchipip.WithSerialPBusMem ++
6256
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad
6357
new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory
6458
new freechips.rocketchip.subsystem.WithNBanks(0) ++

‎generators/chipyard/src/main/scala/config/SpikeConfigs.scala‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,6 @@ class SpikeFastUARTConfig extends Config(
2727
class SpikeUltraFastConfig extends Config(
2828
new chipyard.WithSpikeTCM ++
2929
new chipyard.WithNSpikeCores(1) ++
30-
new testchipip.WithSerialPBusMem ++
3130
new chipyard.config.WithUARTFIFOEntries(128, 128) ++
3231
new chipyard.config.WithMemoryBusFrequency(2) ++
3332
new chipyard.config.WithPeripheryBusFrequency(2) ++
@@ -48,7 +47,6 @@ class SpikeUltraFastDevicesConfig extends Config(
4847

4948
new chipyard.WithSpikeTCM ++
5049
new chipyard.WithNSpikeCores(1) ++
51-
new testchipip.WithSerialPBusMem ++
5250
new chipyard.config.WithUARTFIFOEntries(128, 128) ++
5351
new chipyard.config.WithMemoryBusFrequency(2) ++
5452
new chipyard.config.WithPeripheryBusFrequency(2) ++

‎generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala‎

Lines changed: 0 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -59,27 +59,11 @@ class WithNoDebug extends Config((site, here, up) => {
5959
case DebugModuleKey => None
6060
})
6161

62-
class WithTLSerialLocation(masterWhere: TLBusWrapperLocation, slaveWhere: TLBusWrapperLocation) extends Config((site, here, up) => {
63-
case SerialTLAttachKey => up(SerialTLAttachKey, site).copy(masterWhere = masterWhere, slaveWhere = slaveWhere)
64-
})
65-
6662
class WithTLBackingMemory extends Config((site, here, up) => {
6763
case ExtMem => None // disable AXI backing memory
6864
case ExtTLMem => up(ExtMem, site) // enable TL backing memory
6965
})
7066

71-
class WithSerialTLBackingMemory extends Config((site, here, up) => {
72-
case ExtMem => None
73-
case SerialTLKey => up(SerialTLKey, site).map { k => k.copy(
74-
memParams = {
75-
val memPortParams = up(ExtMem, site).get
76-
require(memPortParams.nMemoryChannels == 1)
77-
memPortParams.master
78-
},
79-
isMemoryDevice = true
80-
)}
81-
})
82-
8367
class WithExtMemIdBits(n: Int) extends Config((site, here, up) => {
8468
case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(idBits = n)))
8569
})

‎generators/chipyard/src/main/scala/example/FlatTestHarness.scala‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -40,9 +40,9 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
4040

4141
// Serialized TL
4242
val sVal = p(SerialTLKey).get
43-
require(sVal.axiMemOverSerialTLParams.isDefined)
44-
require(sVal.isMemoryDevice)
45-
val axiDomainParams = sVal.axiMemOverSerialTLParams.get
43+
val serialTLManagerParams = sVal.serialTLManagerParams.get
44+
val axiDomainParams = serialTLManagerParams.axiMemOverSerialTLParams.get
45+
require(serialTLManagerParams.isMemoryDevice)
4646
val memFreq = axiDomainParams.getMemFrequency(lazyDut.system)
4747

4848
withClockAndReset(clock, reset) {
@@ -59,9 +59,9 @@ class FlatTestHarness(implicit val p: Parameters) extends Module {
5959
io.success := SimTSI.connect(Some(harnessMultiClockAXIRAM.module.io.tsi), clock, reset)
6060

6161
// connect SimDRAM from the AXI port coming from the harness multi clock axi ram
62-
(harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) =>
63-
val memSize = sVal.memParams.size
64-
val memBase = sVal.memParams.base
62+
(harnessMultiClockAXIRAM.mem_axi4.get zip harnessMultiClockAXIRAM.memNode.get.edges.in).map { case (axi_port, edge) =>
63+
val memSize = serialTLManagerParams.memParams.size
64+
val memBase = serialTLManagerParams.memParams.base
6565
val lineSize = p(CacheBlockBytes)
6666
val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), memBase, edge.bundle)).suggestName("simdram")
6767
mem.io.axi <> axi_port.bits

‎generators/chipyard/src/main/scala/harness/HarnessBinders.scala‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -145,9 +145,9 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({
145145
implicit val p = chipyard.iobinders.GetSystemParameters(system)
146146

147147
p(SerialTLKey).map({ sVal =>
148-
require(sVal.axiMemOverSerialTLParams.isDefined)
149-
val axiDomainParams = sVal.axiMemOverSerialTLParams.get
150-
require(sVal.isMemoryDevice)
148+
val serialTLManagerParams = sVal.serialTLManagerParams.get
149+
val axiDomainParams = serialTLManagerParams.axiMemOverSerialTLParams.get
150+
require(serialTLManagerParams.isMemoryDevice)
151151

152152
val memFreq = axiDomainParams.getMemFrequency(system.asInstanceOf[HasTileLinkLocations])
153153

@@ -167,9 +167,9 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({
167167
when (success) { th.success := true.B }
168168

169169
// connect SimDRAM from the AXI port coming from the harness multi clock axi ram
170-
(harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) =>
171-
val memSize = sVal.memParams.size
172-
val memBase = sVal.memParams.base
170+
(harnessMultiClockAXIRAM.mem_axi4.get zip harnessMultiClockAXIRAM.memNode.get.edges.in).map { case (axi_port, edge) =>
171+
val memSize = serialTLManagerParams.memParams.size
172+
val memBase = serialTLManagerParams.memParams.base
173173
val lineSize = p(CacheBlockBytes)
174174
val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), memBase, edge.bundle)).suggestName("simdram")
175175
mem.io.axi <> axi_port.bits

‎generators/firechip/src/main/scala/BridgeBinders.scala‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -113,10 +113,9 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({
113113
implicit val p = GetSystemParameters(system)
114114

115115
p(SerialTLKey).map({ sVal =>
116-
require(sVal.axiMemOverSerialTLParams.isDefined)
117-
val axiDomainParams = sVal.axiMemOverSerialTLParams.get
118-
require(sVal.isMemoryDevice)
119-
116+
val serialTLManagerParams = sVal.serialTLManagerParams.get
117+
val axiDomainParams = serialTLManagerParams.axiMemOverSerialTLParams.get
118+
require(serialTLManagerParams.isMemoryDevice)
120119
val memFreq = axiDomainParams.getMemFrequency(system.asInstanceOf[HasTileLinkLocations])
121120

122121
ports.map({ port =>
@@ -137,7 +136,7 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({
137136
TSIBridge(th.buildtopClock, harnessMultiClockAXIRAM.module.io.tsi, Some(MainMemoryConsts.globalName), th.buildtopReset.asBool)
138137

139138
// connect SimAxiMem
140-
(harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi4, edge) =>
139+
(harnessMultiClockAXIRAM.mem_axi4.get zip harnessMultiClockAXIRAM.memNode.get.edges.in).map { case (axi4, edge) =>
141140
val nastiKey = NastiParameters(axi4.bits.r.bits.data.getWidth,
142141
axi4.bits.ar.bits.addr.getWidth,
143142
axi4.bits.ar.bits.id.getWidth)

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