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beginning the full shift to SystemVerilog: change fpga Makefile, use … #53

beginning the full shift to SystemVerilog: change fpga Makefile, use …

beginning the full shift to SystemVerilog: change fpga Makefile, use … #53

Triggered via push November 6, 2024 18:30
Status Failure
Total duration 4m 31s
Artifacts 6

gds.yaml

on: push
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1 error
gl_test
Process completed with exit code 1.

Artifacts

Produced during runtime
Name Size Digest
GDS_logs Expired
10.2 MB
sha256:a9f101cae6dafc781f03508b38fc235b7bb9d871ad526e75e6412276de39ca25
gatelevel_test_vcd Expired
19.8 KB
sha256:12f239168a65a37baadf4e5cd65dc347b06eab4cb9ad80b658bdc0602b146e4d
gds_render Expired
184 KB
sha256:3456e2311774674bc646798ada395235ae183732373baf9c47081e3cc739ff28
github-pages Expired
1.07 MB
sha256:fa2c558d078eb9bfa42c9f1d3a1b114938ed8f0fb0325944f8358a0e3aa9b7d2
precheck_reports Expired
6.13 KB
sha256:09ca3a13245bcc8dfd5e67d4ec1b0a79bef0830f55d65627687371574073998d
tt_submission Expired
346 KB
sha256:986d90fdd4d8002f26f9005196fb34fb1a919d98240cbe333b4e0addeeb323db