Merge pull request #1358 from slaclab/PgpRxVcFifo-update

Fixed Github CI for cocotb v2 + PgpRxVcFifo.vhd Update

Author: ruck314

axi/axi-stream/ruckus.tcl

@@ -6,4 +6,4 @@ loadSource -lib surf -dir "$::DIR_PATH/rtl"
 loadSource -lib surf -dir "$::DIR_PATH/ip_integrator"
 
 # Load Simulation
-loadSource -lib surf -sim_only -dir "$::DIR_PATH/tb"
+loadSource -lib surf -sim_only -dir "$::DIR_PATH/tb" -fileType "VHDL 2008"

axi/axi-stream/tb/AxiStreamPipelineTb.vhd

@@ -17,6 +17,9 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.std_logic_arith.all;
 
+library std;
+use std.env.all;
+
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiStreamPkg.all;
@@ -226,15 +229,21 @@ begin
       end if;
    end process seq;
 
-   process(failed, passed)
+   ---------------------
+   -- Report the Results
+   ---------------------
+   process(clk)
    begin
-      if failed = '1' then
-         assert false
-            report "Simulation Failed!" severity failure;
-      end if;
-      if passed = '1' then
-         assert false
-            report "Simulation Passed!" severity note;
+      if rising_edge(clk) then
+         if (failed = '1') then
+            assert false
+               report "Simulation Failed!" severity failure;
+         end if;
+         if (passed = '1') then
+            assert false
+               report "Simulation Passed!" severity note;
+            std.env.finish;
+         end if;
       end if;
    end process;
 

axi/axi-stream/tb/AxiStreamPkgTb.vhd

@@ -17,6 +17,9 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.std_logic_arith.all;
 
+library std;
+use std.env.all;
+
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiStreamPkg.all;
@@ -156,15 +159,21 @@ begin
       end if;
    end process seq;
 
-   process(failed, passed)
+   ---------------------
+   -- Report the Results
+   ---------------------
+   process(clk)
    begin
-      if failed = '1' then
-         assert false
-            report "Simulation Failed!" severity failure;
-      end if;
-      if passed = '1' then
-         assert false
-            report "Simulation Passed!" severity note;
+      if rising_edge(clk) then
+         if (failed = '1') then
+            assert false
+               report "Simulation Failed!" severity failure;
+         end if;
+         if (passed = '1') then
+            assert false
+               report "Simulation Passed!" severity note;
+            std.env.finish;
+         end if;
       end if;
    end process;
 

axi/axi-stream/tb/AxiStreamResizeTb.vhd

@@ -17,6 +17,8 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.std_logic_arith.all;
 
+library std;
+use std.env.all;
 
 library surf;
 use surf.StdRtlPkg.all;
@@ -287,6 +289,15 @@ begin
                   end if;
                end if;
             end loop;
+            if (failed = '1') then
+               assert false
+                  report "Simulation Failed!" severity failure;
+            end if;
+            if (uAnd(passed) = '1') then
+               assert false
+                  report "Simulation Passed!" severity note;
+               std.env.finish;
+            end if;
          end if;
       end if;
    end process;

axi/axi4/ruckus.tcl

@@ -10,4 +10,4 @@ if {  $::env(VIVADO_VERSION) > 0.0} {
 }
 
 # Load Simulation
-loadSource -lib surf -sim_only -dir "$::DIR_PATH/tb"
+loadSource -lib surf -sim_only -dir "$::DIR_PATH/tb" -fileType "VHDL 2008"

axi/axi4/tb/AxiRamTb.vhd

@@ -17,6 +17,9 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.std_logic_arith.all;
 
+library std;
+use std.env.all;
+
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiPkg.all;
@@ -145,6 +148,7 @@ begin
          if (passed = '1') then
             assert false
                report "Simulation Passed!" severity note;
+            std.env.finish;
          end if;
       end if;
    end process;

axi/axi4/tb/AxiRingBufferTb.vhd

@@ -17,6 +17,9 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.std_logic_arith.all;
 
+library std;
+use std.env.all;
+
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiPkg.all;
@@ -223,14 +226,21 @@ begin
       end if;
    end process seq;
 
-   process(failed, passed)
+   ---------------------
+   -- Report the Results
+   ---------------------
+   process(clk)
    begin
-      if passed = '1' then
-         assert false
-            report "Simulation Passed!" severity note;
-      elsif failed = '1' then
-         assert false
-            report "Simulation Failed!" severity failure;
+      if rising_edge(clk) then
+         if (failed = '1') then
+            assert false
+               report "Simulation Failed!" severity failure;
+         end if;
+         if (passed = '1') then
+            assert false
+               report "Simulation Passed!" severity note;
+            std.env.finish;
+         end if;
       end if;
    end process;
 

axi/dma/ruckus.tcl

@@ -7,4 +7,4 @@ loadSource -lib surf -dir "$::DIR_PATH/rtl/v1"
 loadSource -lib surf -dir "$::DIR_PATH/rtl/v2"
 
 # Load Simulation
-loadSource -lib surf -sim_only -dir "$::DIR_PATH/tb"
+loadSource -lib surf -sim_only -dir "$::DIR_PATH/tb" -fileType "VHDL 2008"

axi/dma/tb/AxiStreamDmaReadTb.vhd

@@ -17,6 +17,8 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
+library std;
+use std.env.all;
 
 library surf;
 use surf.StdRtlPkg.all;
@@ -286,15 +288,21 @@ begin
       end if;
    end process seq;
 
-   process(failed, passed)
+   ---------------------
+   -- Report the Results
+   ---------------------
+   process(clk)
    begin
-      if failed = '1' then
-         assert false
-            report "Simulation Failed!" severity failure;
-      end if;
-      if passed = '1' then
-         assert false
-            report "Simulation Passed!" severity note;
+      if rising_edge(clk) then
+         if (failed = '1') then
+            assert false
+               report "Simulation Failed!" severity failure;
+         end if;
+         if (passed = '1') then
+            assert false
+               report "Simulation Passed!" severity note;
+            std.env.finish;
+         end if;
       end if;
    end process;
 

base/delay/ruckus.tcl

@@ -5,4 +5,4 @@ source $::env(RUCKUS_PROC_TCL)
 loadSource -lib surf -dir "$::DIR_PATH/rtl"
 
 # Load Simulation
-loadSource -lib surf -sim_only -dir "$::DIR_PATH/tb"
+loadSource -lib surf -sim_only -dir "$::DIR_PATH/tb" -fileType "VHDL 2008"