Merge pull request #1347 from slaclab/pre-release

Release Candidate v2.66.0

Author: ruck314

axi/axi-lite/rtl/AxiDualPortRam.vhd

@@ -395,6 +395,9 @@ begin
                -- Next state
                v.state := IDLE_S;
             end if;
+         ----------------------------------------------------------------------
+         when others =>  -- For ASIC designs it is best to declare a 'Default' state which returns to IDLE_S state
+            v := REG_INIT_C;
       ----------------------------------------------------------------------
       end case;
 

axi/axi-lite/rtl/AxiLiteCrossbar.vhd

@@ -275,6 +275,8 @@ begin
                      end if;
                   end if;
                end loop;
+            when others =>  -- For ASIC designs it is best to declare a 'Default' state which returns to S_WAIT_AXI_TXN_S state
+               v := REG_INIT_C;
          end case;
 
          -- Read state machine
@@ -344,6 +346,8 @@ begin
                      end if;
                   end if;
                end loop;
+            when others =>  -- For ASIC designs it is best to declare a 'Default' state which returns to S_WAIT_AXI_TXN_S state
+               v := REG_INIT_C;
          end case;
       end loop;
 
@@ -405,6 +409,8 @@ begin
                   v.master(m).wrValid := '0';
                end if;
 
+            when others =>  -- For ASIC designs it is best to declare a 'Default' state which returns to M_WAIT_REQ_S state
+               v := REG_INIT_C;
          end case;
 
          -- Don't allow baseAddr bits to be overwritten
@@ -459,6 +465,8 @@ begin
                   v.master(m).rdValid := '0';
                end if;
 
+            when others =>  -- For ASIC designs it is best to declare a 'Default' state which returns to M_WAIT_REQ_S state
+               v := REG_INIT_C;
          end case;
 
          -- Don't allow baseAddr bits to be overwritten

axi/axi-lite/rtl/AxiLiteMaster.vhd

@@ -145,6 +145,9 @@ begin
                v.state    := S_IDLE_C;
             end if;
 
+         when others =>  -- For ASIC designs it is best to declare a 'Default' state which returns to S_IDLE_C state
+            v := REG_INIT_C;
+
       end case;
 
       if (RST_ASYNC_G = false and axilRst = RST_POLARITY_G) then

axi/axi-lite/rtl/AxiLiteMasterProxy.vhd

@@ -131,6 +131,10 @@ begin
                -- Next state
                v.state       := READY_S;
             end if;
+         ----------------------------------------------------------------------
+         when others =>  -- For ASIC designs it is best to declare a 'Default' state which returns to READY_S state
+            v := REG_INIT_C;
+      ----------------------------------------------------------------------
       end case;
 
       -- Reset

axi/axi-lite/rtl/AxiLiteRespTimer.vhd

@@ -111,6 +111,9 @@ begin
                -- Decrement the counter
                v.timer := r.timer - 1;
             end if;
+         ----------------------------------------------------------------------
+         when others =>  -- For ASIC designs it is best to declare a 'Default' state which returns to IDLE_S state
+            v := REG_INIT_C;
       ----------------------------------------------------------------------
       end case;
 

axi/axi-lite/rtl/AxiLiteSequencerRam.vhd

@@ -457,6 +457,9 @@ begin
             v.wstrb := (others => '1');
             -- Next state
             v.state := IDLE_S;
+         ----------------------------------------------------------------------
+         when others =>  -- For ASIC designs it is best to declare a 'Default' state which returns to IDLE_S state
+            v := REG_INIT_C;
       ----------------------------------------------------------------------
       end case;
 

axi/axi-lite/rtl/AxiLiteSlave.vhd

@@ -129,6 +129,9 @@ begin
                -- Next state
                v.state := IDLE_S;
             end if;
+         ----------------------------------------------------------------------
+         when others =>  -- For ASIC designs it is best to declare a 'Default' state which returns to IDLE_S state
+            v := REG_INIT_C;
       ----------------------------------------------------------------------
       end case;
 

axi/axi-lite/rtl/AxiLiteWriteFilter.vhd

@@ -184,7 +184,10 @@ begin
                -- Next state
                v.state := IDLE_S;
             end if;
-      ------------------------------------------------------------------------------------
+         ----------------------------------------------------------------------
+         when others =>  -- For ASIC designs it is best to declare a 'Default' state which returns to IDLE_S state
+            v := REG_INIT_C;
+      ----------------------------------------------------------------------
       end case;
 
       -- Synchronous Reset

axi/axi-stream/ip_integrator/MasterAxiStreamIpIntegrator.vhd

@@ -85,7 +85,16 @@ architecture mapping of MasterAxiStreamIpIntegrator is
       "ASSOCIATED_BUSIF " & INTERFACENAME & ", " &
       "ASSOCIATED_RESET " & INTERFACENAME & "_ARESETN";
 
-   signal M_AXIS_Master : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C;
+   constant AXIS_CONFIG_C : AxiStreamConfigType := (
+      TSTRB_EN_C    => (HAS_TSTRB = 1),
+      TDATA_BYTES_C => TDATA_NUM_BYTES,
+      TDEST_BITS_C  => TDEST_WIDTH,
+      TID_BITS_C    => TID_WIDTH,
+      TKEEP_MODE_C  => TKEEP_NORMAL_C,
+      TUSER_BITS_C  => TUSER_WIDTH,
+      TUSER_MODE_C  => TUSER_NORMAL_C);
+
+   signal M_AXIS_Master : AxiStreamMasterType := axiStreamMasterInit(AXIS_CONFIG_C);
    signal M_AXIS_Slave  : AxiStreamSlaveType  := AXI_STREAM_SLAVE_FORCE_C;
 
 begin

axi/axi-stream/ip_integrator/SlaveAxiStreamIpIntegrator.vhd

@@ -85,7 +85,16 @@ architecture mapping of SlaveAxiStreamIpIntegrator is
       "ASSOCIATED_BUSIF " & INTERFACENAME & ", " &
       "ASSOCIATED_RESET " & INTERFACENAME & "_ARESETN";
 
-   signal S_AXIS_Master : AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C;
+   constant AXIS_CONFIG_C : AxiStreamConfigType := (
+      TSTRB_EN_C    => (HAS_TSTRB = 1),
+      TDATA_BYTES_C => TDATA_NUM_BYTES,
+      TDEST_BITS_C  => TDEST_WIDTH,
+      TID_BITS_C    => TID_WIDTH,
+      TKEEP_MODE_C  => TKEEP_NORMAL_C,
+      TUSER_BITS_C  => TUSER_WIDTH,
+      TUSER_MODE_C  => TUSER_NORMAL_C);
+
+   signal S_AXIS_Master : AxiStreamMasterType := axiStreamMasterInit(AXIS_CONFIG_C);
    signal S_AXIS_Slave  : AxiStreamSlaveType  := AXI_STREAM_SLAVE_FORCE_C;
 
 begin