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1. verilog_template verilog_template Public template

   This project demonstrates a scalable format for Verilog including build scripts, design verification, and synthesis.

   Tcl 4 3

2. sky130_schematics sky130_schematics Public

   Verified visual schematics for all SKY130 Cells

   Tcl 10 13

3. labs-with-cva6 labs-with-cva6 Public

   Advanced Architecture Labs with CVA6

   SystemVerilog 65 26

4. ucsbieee/mapache64 ucsbieee/mapache64 Public

   Custom 6502 Video Game Console

   SystemVerilog 11

5. flip_flop_visualizer flip_flop_visualizer Public

   Website to visualize the timing and schematics of flip-flops.

   JavaScript 2

6. thesis thesis Public

   Ethan Sifferman Master's Thesis: "Advancing Synthesizable Verilog/SystemVerilog Education with Open-Source Tools and Autograders"

   TeX 4 1