Merge pull request ARMmbed#7453 from marcuschangarm/fix-nrf52-swi

Fix SWI conflict in SoftDevice for NRF52 series

Author: Cruz Monrreal

targets/TARGET_NORDIC/TARGET_NRF5x/README.md

@@ -143,9 +143,9 @@ The table must be placed in a C compilation file.
 Because each DMA buffer must be at least 5 bytes deep, each buffer is automatically flushed after a certain idle period to ensure low latency and correctness. This idle timeout is implemented using 2 of the 4 channels on RTC instance 2. This leaves RTC0 for the SoftDevice and RTC1 for Mbed tickers.
 
 
-#### SWI2, SWI3, SWI4, and SWI5
+#### SWI0
 
-To minimize the time spend in the highest priority interrupt handler all callbacks to the user provided IRQ handlers are deferred through Software Interrupts running at lowest priority. SWI 2-5 are reserved by the serial implementation.
+To minimize the time spend in the highest priority interrupt handler all callbacks to the user provided IRQ handlers are deferred through Software Interrupts running at lowest priority. SWI0 is reserved by the serial implementation.
 
 
 #### Asserts
@@ -156,13 +156,14 @@ The SDK file `mbed-os/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/librari
 The assert handler is defined in mbed-os/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5x/source/btle/btle.cpp : assert_nrf_callback() which forwards assert failures to thye mbed error() handler.
 
 
-
 #### Limitations
 
  * The UARTE hardware only supports 8-bit, None/Even parity, and 1 stop bit.
  * The asynchronous read and write implementation currently only support 255 byte transfers.
  * The EasyDMA hardware can only read from RAM, which means all Tx buffers must reside in RAM. If a Tx buffer residing in flash is passed to the asynchronous write function, the function will try to copy the Tx buffer to a temporary internal buffer and transmit the data from there.
  * It is not possible to do an asynchronous write from flash and receive non-asynchronously at the same time since the non-asynchronous receive buffer is being used as the temporary transmission buffer.
+ * The driver will flush the DMA buffer after a configurable timeout. During this process the UART will be halted and therefor unable to receive data. Hardware flow control should be enabled to avoid missing any data during this window.
+
 
 ## SoftDevice