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Add OSPI Flash support #2

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Add OSPI Flash support #2

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464a752
Add OSPI Flash support
jeremy-baker Dec 15, 2025
71167e2
Update to FSP 6.3.0
jeremy-baker Jan 7, 2026
5f520fa
Remove custom placement of LVGL work memory
jeremy-baker Jan 8, 2026
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18 changes: 12 additions & 6 deletions .cproject
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11 changes: 0 additions & 11 deletions .gitignore
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Original file line number Diff line number Diff line change
Expand Up @@ -3,17 +3,6 @@
/ra_gen
/ra_cfg
ra/*
!ra/fsp
ra/fsp/*
!ra/fsp/src
ra/fsp/src/*
!ra/fsp/src/r_drw
ra/fsp/src/r_drw/*
!ra/fsp/src/r_dtc
ra/fsp/src/r_dtc/*
!ra/fsp/src/r_drw/r_drw_memory.c
!ra/fsp/src/r_dtc/r_dtc.c
src/lvgl/*

/JLinkLog.log
/build/
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14 changes: 14 additions & 0 deletions .secure_azone
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Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,13 @@
<rzone name="R7KA8D2KFLCAC.rzone"/>
<partition>
<peripheral name="PORT1.CPU0" group="PORT">
<slot name="P100.CPU0" secure="true"/>
<slot name="P101.CPU0" secure="true"/>
<slot name="P102.CPU0" secure="true"/>
<slot name="P103.CPU0" secure="true"/>
<slot name="P104.CPU0" secure="true"/>
<slot name="P105.CPU0" secure="true"/>
<slot name="P106.CPU0" secure="true"/>
<slot name="P111.CPU0" secure="true"/>
<slot name="P112.CPU0" secure="true"/>
<slot name="P113.CPU0" secure="true"/>
Expand Down Expand Up @@ -56,9 +63,15 @@
<slot name="P715.CPU0" secure="true"/>
</peripheral>
<peripheral name="PORT8.CPU0" group="PORT">
<slot name="P800.CPU0" secure="true"/>
<slot name="P801.CPU0" secure="true"/>
<slot name="P802.CPU0" secure="true"/>
<slot name="P803.CPU0" secure="true"/>
<slot name="P804.CPU0" secure="true"/>
<slot name="P805.CPU0" secure="true"/>
<slot name="P806.CPU0" secure="true"/>
<slot name="P807.CPU0" secure="true"/>
<slot name="P808.CPU0" secure="true"/>
<slot name="P813.CPU0" secure="true"/>
</peripheral>
<peripheral name="PORT9.CPU0" group="PORT">
Expand Down Expand Up @@ -129,6 +142,7 @@
</peripheral>
<peripheral name="IIC1.CPU0" group="IIC" security="s"/>
<peripheral name="GLCDC.CPU0" security="s"/>
<peripheral name="DMA_DMAC0.CPU0" group="DMA_DMAC" security="s"/>
<peripheral name="ICU.CPU0">
<slot name="IRQ0.CPU0" secure="true"/>
<slot name="IRQ1.CPU0" secure="true"/>
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8 changes: 4 additions & 4 deletions .secure_rzone
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Expand Up @@ -20,13 +20,13 @@
<memory name="OPTION_SETTING_OFS0" type="ROM" start="0x02c9f040" size="0x00000004" access="r" security="s" info="Option Function Select Register 0"/>
<memory name="OPTION_SETTING_OFS2" type="ROM" start="0x02c9f044" size="0x00000004" access="r" security="s" info="Option Function Select Register 2"/>
<memory name="OPTION_SETTING_SAS" type="ROM" start="0x02c9f074" size="0x00000004" access="r" security="s" info="Startup Area Setting Register"/>
<memory name="OPTION_SETTING_OFS1" type="ROM" start="0x12c9f4c0" size="0x00000004" access="r" security="n" info="Option Function Select Register 1"/>
<memory name="OPTION_SETTING_OFS1" type="ROM" start="0x12c9f4c0" size="0x00000004" access="r" security="" info="Option Function Select Register 1"/>
<memory name="OPTION_SETTING_OFS1_SEC" type="ROM" start="0x02c9f0c0" size="0x00000004" access="r" security="s" info="Option Function Select Register 1 Secure"/>
<memory name="OPTION_SETTING_OFS1_SEL" type="ROM" start="0x02c9f120" size="0x00000004" access="r" security="s" info="OFS1 Security Attribution"/>
<memory name="OPTION_SETTING_OFS3" type="ROM" start="0x12c9f4c4" size="0x00000004" access="r" security="n" info="Option Function Select Register 3"/>
<memory name="OPTION_SETTING_OFS3" type="ROM" start="0x12c9f4c4" size="0x00000004" access="r" security="" info="Option Function Select Register 3"/>
<memory name="OPTION_SETTING_OFS3_SEC" type="ROM" start="0x02c9f0c4" size="0x00000004" access="r" security="s" info="Option Function Select Register 3 Secure"/>
<memory name="OPTION_SETTING_OFS3_SEL" type="ROM" start="0x02c9f124" size="0x00000004" access="r" security="s" info="OFS3 Security Attribution"/>
<memory name="OPTION_SETTING_BPS" type="ROM" start="0x12c9f600" size="0x00000080" access="r" security="n" info="Block Protect Setting Register"/>
<memory name="OPTION_SETTING_BPS" type="ROM" start="0x12c9f600" size="0x00000080" access="r" security="" info="Block Protect Setting Register"/>
<memory name="OPTION_SETTING_BPS_SEC" type="ROM" start="0x02c9f200" size="0x00000080" access="r" security="s" info="Block Protect Setting Register Secure"/>
<memory name="OPTION_SETTING_OTP_FSBLCTRL0" type="ROM" start="0x02e07600" size="0x00000004" access="r" security="s" info="FSBL Control Register 0"/>
<memory name="OPTION_SETTING_OTP_FSBLCTRL1" type="ROM" start="0x02e07604" size="0x00000004" access="r" security="s" info="FSBL Control Register 1"/>
Expand All @@ -41,7 +41,7 @@
<memory name="OPTION_SETTING_OTP_SACC03" type="ROM" start="0x02e07680" size="0x00000004" access="r" security="s" info="Start Address of Code Certificate 03"/>
<memory name="OPTION_SETTING_OTP_SACC13" type="ROM" start="0x02e07690" size="0x00000004" access="r" security="s" info="Start Address of Code Certificate 13"/>
<memory name="OPTION_SETTING_OTP_PBPS_SEC" type="ROM" start="0x02e17700" size="0x00000080" access="r" security="s" info="Permanent Block Protect Setting Register Secure"/>
<memory name="OPTION_SETTING_OTP_PBPS" type="ROM" start="0x12e17780" size="0x00000080" access="r" security="n" info="Permanent Block Protect Setting Register"/>
<memory name="OPTION_SETTING_OTP_PBPS" type="ROM" start="0x12e17780" size="0x00000080" access="r" security="" info="Permanent Block Protect Setting Register"/>
<memory name="OPTION_SETTING_OTP_ZHUK" type="ROM" start="0x02e17920" size="0x00000004" access="r" security="s" info="Zerorization HUK Register"/>
<memory name="ITCM_NS" type="RAM" start="0x10000000" physical="0x00000000" size="0x00020000" access="rwx" security="n" Pname="CPU0" info="internal instruction tightly coupled memory @nsAlign:0x00002000"/>
<memory name="ITCM" type="RAM" start="0x00000000" size="0x00020000" access="rwx" security="s" Pname="CPU0" info="internal instruction tightly coupled memory"/>
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