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[SPARC][IAS] Add support for %uhi and %ulo extensions #94246

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Merged
merged 4 commits into from
Jun 9, 2024
Merged

[SPARC][IAS] Add support for %uhi and %ulo extensions #94246

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04bfa20
[𝘀𝗽𝗿] changes to main this commit is based on
koachan Jun 3, 2024
0fc914c
[𝘀𝗽𝗿] initial version
koachan Jun 3, 2024
6c827e0
[𝘀𝗽𝗿] landed version
koachan Jun 9, 2024
92c89ee
[𝘀𝗽𝗿] landed version
koachan Jun 9, 2024
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78 changes: 40 additions & 38 deletions llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -93,44 +93,46 @@ bool SparcMCExpr::printVariantKind(raw_ostream &OS, VariantKind Kind)
SparcMCExpr::VariantKind SparcMCExpr::parseVariantKind(StringRef name)
{
return StringSwitch<SparcMCExpr::VariantKind>(name)
.Case("lo", VK_Sparc_LO)
.Case("hi", VK_Sparc_HI)
.Case("h44", VK_Sparc_H44)
.Case("m44", VK_Sparc_M44)
.Case("l44", VK_Sparc_L44)
.Case("hh", VK_Sparc_HH)
.Case("hm", VK_Sparc_HM)
.Case("lm", VK_Sparc_LM)
.Case("pc22", VK_Sparc_PC22)
.Case("pc10", VK_Sparc_PC10)
.Case("got22", VK_Sparc_GOT22)
.Case("got10", VK_Sparc_GOT10)
.Case("got13", VK_Sparc_GOT13)
.Case("r_disp32", VK_Sparc_R_DISP32)
.Case("tgd_hi22", VK_Sparc_TLS_GD_HI22)
.Case("tgd_lo10", VK_Sparc_TLS_GD_LO10)
.Case("tgd_add", VK_Sparc_TLS_GD_ADD)
.Case("tgd_call", VK_Sparc_TLS_GD_CALL)
.Case("tldm_hi22", VK_Sparc_TLS_LDM_HI22)
.Case("tldm_lo10", VK_Sparc_TLS_LDM_LO10)
.Case("tldm_add", VK_Sparc_TLS_LDM_ADD)
.Case("tldm_call", VK_Sparc_TLS_LDM_CALL)
.Case("tldo_hix22", VK_Sparc_TLS_LDO_HIX22)
.Case("tldo_lox10", VK_Sparc_TLS_LDO_LOX10)
.Case("tldo_add", VK_Sparc_TLS_LDO_ADD)
.Case("tie_hi22", VK_Sparc_TLS_IE_HI22)
.Case("tie_lo10", VK_Sparc_TLS_IE_LO10)
.Case("tie_ld", VK_Sparc_TLS_IE_LD)
.Case("tie_ldx", VK_Sparc_TLS_IE_LDX)
.Case("tie_add", VK_Sparc_TLS_IE_ADD)
.Case("tle_hix22", VK_Sparc_TLS_LE_HIX22)
.Case("tle_lox10", VK_Sparc_TLS_LE_LOX10)
.Case("hix", VK_Sparc_HIX22)
.Case("lox", VK_Sparc_LOX10)
.Case("gdop_hix22", VK_Sparc_GOTDATA_HIX22)
.Case("gdop_lox10", VK_Sparc_GOTDATA_LOX10)
.Case("gdop", VK_Sparc_GOTDATA_OP)
.Default(VK_Sparc_None);
.Case("lo", VK_Sparc_LO)
.Case("hi", VK_Sparc_HI)
.Case("h44", VK_Sparc_H44)
.Case("m44", VK_Sparc_M44)
.Case("l44", VK_Sparc_L44)
.Case("hh", VK_Sparc_HH)
.Case("uhi", VK_Sparc_HH) // Nonstandard GNU extension
.Case("hm", VK_Sparc_HM)
.Case("ulo", VK_Sparc_HM) // Nonstandard GNU extension
.Case("lm", VK_Sparc_LM)
.Case("pc22", VK_Sparc_PC22)
.Case("pc10", VK_Sparc_PC10)
.Case("got22", VK_Sparc_GOT22)
.Case("got10", VK_Sparc_GOT10)
.Case("got13", VK_Sparc_GOT13)
.Case("r_disp32", VK_Sparc_R_DISP32)
.Case("tgd_hi22", VK_Sparc_TLS_GD_HI22)
.Case("tgd_lo10", VK_Sparc_TLS_GD_LO10)
.Case("tgd_add", VK_Sparc_TLS_GD_ADD)
.Case("tgd_call", VK_Sparc_TLS_GD_CALL)
.Case("tldm_hi22", VK_Sparc_TLS_LDM_HI22)
.Case("tldm_lo10", VK_Sparc_TLS_LDM_LO10)
.Case("tldm_add", VK_Sparc_TLS_LDM_ADD)
.Case("tldm_call", VK_Sparc_TLS_LDM_CALL)
.Case("tldo_hix22", VK_Sparc_TLS_LDO_HIX22)
.Case("tldo_lox10", VK_Sparc_TLS_LDO_LOX10)
.Case("tldo_add", VK_Sparc_TLS_LDO_ADD)
.Case("tie_hi22", VK_Sparc_TLS_IE_HI22)
.Case("tie_lo10", VK_Sparc_TLS_IE_LO10)
.Case("tie_ld", VK_Sparc_TLS_IE_LD)
.Case("tie_ldx", VK_Sparc_TLS_IE_LDX)
.Case("tie_add", VK_Sparc_TLS_IE_ADD)
.Case("tle_hix22", VK_Sparc_TLS_LE_HIX22)
.Case("tle_lox10", VK_Sparc_TLS_LE_LOX10)
.Case("hix", VK_Sparc_HIX22)
.Case("lox", VK_Sparc_LOX10)
.Case("gdop_hix22", VK_Sparc_GOTDATA_HIX22)
.Case("gdop_lox10", VK_Sparc_GOTDATA_LOX10)
.Case("gdop", VK_Sparc_GOTDATA_OP)
.Default(VK_Sparc_None);
}

Sparc::Fixups SparcMCExpr::getFixupKind(SparcMCExpr::VariantKind Kind) {
Expand Down
11 changes: 8 additions & 3 deletions llvm/lib/Target/Sparc/SparcInstrAliases.td
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Original file line number Diff line number Diff line change
Expand Up @@ -560,11 +560,16 @@ def : InstAlias<"mov $simm13, %tbr", (WRTBRri G0, simm13Op:$simm13), 0>;

// End of Section A.3

// or imm, reg, rd -> or reg, imm, rd
// Nonstandard GNU extension.
let EmitPriority = 0 in

// Nonstandard GNU extensions.
let EmitPriority = 0 in {
// or imm, reg, rd -> or reg, imm, rd
def : InstAlias<"or $simm13, $rs1, $rd", (ORri IntRegs:$rd, IntRegs:$rs1, simm13Op:$simm13)>;

// addc/addx imm, reg, rd -> or reg, imm, rd
def : InstAlias<"addx $simm13, $rs1, $rd", (ADDCri IntRegs:$rd, IntRegs:$rs1, simm13Op:$simm13)>;
}

// wr reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
// (aka: omit the first arg when it's g0. This is not in the manual, but is
// supported by gnu and solaris as)
Expand Down
10 changes: 10 additions & 0 deletions llvm/test/MC/Sparc/sparc-relocations.s
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Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,8 @@
! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_M44 sym
! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_L44 sym
! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_HH22 sym
! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_HH22 sym
! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_HM10 sym
! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_HM10 sym
! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_LM22 sym
! CHECK-OBJ-NEXT: 0x{{[0-9,A-F]+}} R_SPARC_13 sym
Expand Down Expand Up @@ -49,10 +51,18 @@
! CHECK-NEXT: ! fixup A - offset: 0, value: %hh(sym), kind: fixup_sparc_hh
sethi %hh(sym), %l0

! CHECK: sethi %hh(sym), %l0 ! encoding: [0x21,0b00AAAAAA,A,A]
! CHECK-NEXT: ! fixup A - offset: 0, value: %hh(sym), kind: fixup_sparc_hh
sethi %uhi(sym), %l0

! CHECK: or %g1, %hm(sym), %g3 ! encoding: [0x86,0x10,0b011000AA,A]
! CHECK-NEXT: ! fixup A - offset: 0, value: %hm(sym), kind: fixup_sparc_hm
or %g1, %hm(sym), %g3

! CHECK: or %g1, %hm(sym), %g3 ! encoding: [0x86,0x10,0b011000AA,A]
! CHECK-NEXT: ! fixup A - offset: 0, value: %hm(sym), kind: fixup_sparc_hm
or %g1, %ulo(sym), %g3

! CHECK: sethi %lm(sym), %l0 ! encoding: [0x21,0b00AAAAAA,A,A]
! CHECK-NEXT: ! fixup A - offset: 0, value: %lm(sym), kind: fixup_sparc_lm
sethi %lm(sym), %l0
Expand Down
10 changes: 10 additions & 0 deletions llvm/test/MC/Sparc/sparcv9-instructions.s
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Expand Up @@ -6,6 +6,16 @@
! V9: addx %g2, %g1, %g3 ! encoding: [0x86,0x40,0x80,0x01]
addc %g2, %g1, %g3

! V8: error: invalid instruction mnemonic
! V8-NEXT: addc %g2, 1, %g3
! V9: addx %g2, 1, %g3 ! encoding: [0x86,0x40,0xa0,0x01]
addc %g2, 1, %g3

! V8: error: invalid instruction mnemonic
! V8-NEXT: addc 1, %g2, %g3
! V9: addx %g2, 1, %g3 ! encoding: [0x86,0x40,0xa0,0x01]
addc 1, %g2, %g3

! V8: error: invalid instruction mnemonic
! V8-NEXT: addccc %g1, %g2, %g3
! V9: addxcc %g1, %g2, %g3 ! encoding: [0x86,0xc0,0x40,0x02]
Expand Down