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release/18.x: [RISCV][ISel] Fix types in tryFoldSelectIntoOp (#90659) #90682

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Merged
merged 1 commit into from
May 1, 2024
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release/18.x: [RISCV][ISel] Fix types in tryFoldSelectIntoOp (#90659) #90682

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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -14559,7 +14559,7 @@ static SDValue tryFoldSelectIntoOp(SDNode *N, SelectionDAG &DAG,
EVT VT = N->getValueType(0);
SDLoc DL(N);
SDValue OtherOp = TrueVal.getOperand(1 - OpToFold);
EVT OtherOpVT = OtherOp->getValueType(0);
EVT OtherOpVT = OtherOp.getValueType();
SDValue IdentityOperand =
DAG.getNeutralElement(Opc, DL, OtherOpVT, N->getFlags());
if (!Commutative)
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19 changes: 19 additions & 0 deletions llvm/test/CodeGen/RISCV/pr90652.ll
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@@ -0,0 +1,19 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc < %s -mtriple=riscv64 | FileCheck %s

define i1 @test(i64 %x, i1 %cond1, i1 %cond2) {
; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi a3, a0, 1
; CHECK-NEXT: slt a0, a3, a0
; CHECK-NEXT: not a1, a1
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: or a0, a2, a0
; CHECK-NEXT: ret
entry:
%sadd = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %x, i64 1)
%ov = extractvalue { i64, i1 } %sadd, 1
%or = or i1 %cond2, %ov
%sel = select i1 %cond1, i1 %cond2, i1 %or
ret i1 %sel
}