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[AArch64] Only apply bool vector bitcast opt if result is scalar #81256

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Merged
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Feb 12, 2024
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[AArch64] Only apply bool vector bitcast opt if result is scalar #81256

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3 changes: 2 additions & 1 deletion llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -24615,7 +24615,8 @@ void AArch64TargetLowering::ReplaceBITCASTResults(
return;
}

if (SrcVT.isVector() && SrcVT.getVectorElementType() == MVT::i1)
if (SrcVT.isVector() && SrcVT.getVectorElementType() == MVT::i1 &&
!VT.isVector())
return replaceBoolVectorBitcast(N, Results, DAG);

if (VT != MVT::i16 || (SrcVT != MVT::f16 && SrcVT != MVT::bf16))
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28 changes: 28 additions & 0 deletions llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
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Expand Up @@ -489,3 +489,31 @@ define i6 @no_combine_illegal_num_elements(<6 x i32> %vec) {
%bitmask = bitcast <6 x i1> %cmp_result to i6
ret i6 %bitmask
}

; Only apply the combine when casting a vector to a scalar.
define <2 x i8> @vector_to_vector_cast(<16 x i1> %arg) nounwind {
; CHECK-LABEL: vector_to_vector_cast:
; CHECK: ; %bb.0:
; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: shl.16b v0, v0, #7
; CHECK-NEXT: Lloh36:
; CHECK-NEXT: adrp x8, lCPI20_0@PAGE
; CHECK-NEXT: Lloh37:
; CHECK-NEXT: ldr q1, [x8, lCPI20_0@PAGEOFF]
; CHECK-NEXT: add x8, sp, #14
; CHECK-NEXT: cmlt.16b v0, v0, #0
; CHECK-NEXT: and.16b v0, v0, v1
; CHECK-NEXT: ext.16b v1, v0, v0, #8
; CHECK-NEXT: zip1.16b v0, v0, v1
; CHECK-NEXT: addv.8h h0, v0
; CHECK-NEXT: str h0, [sp, #14]
; CHECK-NEXT: ld1.b { v0 }[0], [x8]
; CHECK-NEXT: orr x8, x8, #0x1
; CHECK-NEXT: ld1.b { v0 }[4], [x8]
; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: add sp, sp, #16
; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh36, Lloh37
%bc = bitcast <16 x i1> %arg to <2 x i8>
ret <2 x i8> %bc
}