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[GlobalISel][AArch64] Add saturated truncate tests. NFC #154329

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Merged
jyli0116 merged 1 commit into from
Aug 19, 2025
Merged

[GlobalISel][AArch64] Add saturated truncate tests. NFC #154329

jyli0116 merged 1 commit into from
Aug 19, 2025

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@jyli0116 jyli0116 commented Aug 19, 2025

Added GlobalISel tests for saturated truncate.

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llvmbot commented Aug 19, 2025

@llvm/pr-subscribers-backend-aarch64

Author: None (jyli0116)

Changes

Added GlobalISel tests for saturated truncate.

Patch is 306.25 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/154329.diff

4 Files Affected:

  • (modified) llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll (+3765-672)
  • (modified) llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll (+247-504)
  • (modified) llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll (+205-423)
  • (modified) llvm/test/CodeGen/AArch64/qmovn.ll (+576-192)
diff --git a/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll b/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
index 83ea72c865283..d205b133fbe8c 100644
--- a/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
@@ -1,15 +1,51 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT
-; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
+; RUN: llc < %s -mtriple=aarch64 -global-isel=0| FileCheck %s --check-prefixes=CHECK,CHECK-CVT,CHECK-CVT-SD
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-FP16-SD
+; RUN: llc < %s -mtriple=aarch64 -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT,CHECK-CVT-GI
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-FP16-GI
 
 ; i32 saturate
 
 define <2 x i32> @stest_f64i32(<2 x double> %x) {
-; CHECK-LABEL: stest_f64i32:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
-; CHECK-NEXT:    sqxtn v0.2s, v0.2d
-; CHECK-NEXT:    ret
+; CHECK-CVT-SD-LABEL: stest_f64i32:
+; CHECK-CVT-SD:       // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-CVT-SD-NEXT:    sqxtn v0.2s, v0.2d
+; CHECK-CVT-SD-NEXT:    ret
+;
+; CHECK-FP16-SD-LABEL: stest_f64i32:
+; CHECK-FP16-SD:       // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-FP16-SD-NEXT:    sqxtn v0.2s, v0.2d
+; CHECK-FP16-SD-NEXT:    ret
+;
+; CHECK-CVT-GI-LABEL: stest_f64i32:
+; CHECK-CVT-GI:       // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT:    adrp x8, .LCPI0_1
+; CHECK-CVT-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI0_1]
+; CHECK-CVT-GI-NEXT:    adrp x8, .LCPI0_0
+; CHECK-CVT-GI-NEXT:    cmgt v2.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT:    bif v0.16b, v1.16b, v2.16b
+; CHECK-CVT-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI0_0]
+; CHECK-CVT-GI-NEXT:    cmgt v2.2d, v0.2d, v1.2d
+; CHECK-CVT-GI-NEXT:    bif v0.16b, v1.16b, v2.16b
+; CHECK-CVT-GI-NEXT:    xtn v0.2s, v0.2d
+; CHECK-CVT-GI-NEXT:    ret
+;
+; CHECK-FP16-GI-LABEL: stest_f64i32:
+; CHECK-FP16-GI:       // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT:    adrp x8, .LCPI0_1
+; CHECK-FP16-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI0_1]
+; CHECK-FP16-GI-NEXT:    adrp x8, .LCPI0_0
+; CHECK-FP16-GI-NEXT:    cmgt v2.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT:    bif v0.16b, v1.16b, v2.16b
+; CHECK-FP16-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI0_0]
+; CHECK-FP16-GI-NEXT:    cmgt v2.2d, v0.2d, v1.2d
+; CHECK-FP16-GI-NEXT:    bif v0.16b, v1.16b, v2.16b
+; CHECK-FP16-GI-NEXT:    xtn v0.2s, v0.2d
+; CHECK-FP16-GI-NEXT:    ret
 entry:
   %conv = fptosi <2 x double> %x to <2 x i64>
   %0 = icmp slt <2 x i64> %conv, <i64 2147483647, i64 2147483647>
@@ -21,15 +57,43 @@ entry:
 }
 
 define <2 x i32> @utest_f64i32(<2 x double> %x) {
-; CHECK-LABEL: utest_f64i32:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov d1, v0.d[1]
-; CHECK-NEXT:    fcvtzu w8, d0
-; CHECK-NEXT:    fcvtzu w9, d1
-; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    mov v0.s[1], w9
-; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT:    ret
+; CHECK-CVT-SD-LABEL: utest_f64i32:
+; CHECK-CVT-SD:       // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT:    mov d1, v0.d[1]
+; CHECK-CVT-SD-NEXT:    fcvtzu w8, d0
+; CHECK-CVT-SD-NEXT:    fcvtzu w9, d1
+; CHECK-CVT-SD-NEXT:    fmov s0, w8
+; CHECK-CVT-SD-NEXT:    mov v0.s[1], w9
+; CHECK-CVT-SD-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-CVT-SD-NEXT:    ret
+;
+; CHECK-FP16-SD-LABEL: utest_f64i32:
+; CHECK-FP16-SD:       // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT:    mov d1, v0.d[1]
+; CHECK-FP16-SD-NEXT:    fcvtzu w8, d0
+; CHECK-FP16-SD-NEXT:    fcvtzu w9, d1
+; CHECK-FP16-SD-NEXT:    fmov s0, w8
+; CHECK-FP16-SD-NEXT:    mov v0.s[1], w9
+; CHECK-FP16-SD-NEXT:    // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-SD-NEXT:    ret
+;
+; CHECK-CVT-GI-LABEL: utest_f64i32:
+; CHECK-CVT-GI:       // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-CVT-GI-NEXT:    fcvtzu v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT:    cmhi v2.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT:    bif v0.16b, v1.16b, v2.16b
+; CHECK-CVT-GI-NEXT:    xtn v0.2s, v0.2d
+; CHECK-CVT-GI-NEXT:    ret
+;
+; CHECK-FP16-GI-LABEL: utest_f64i32:
+; CHECK-FP16-GI:       // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-FP16-GI-NEXT:    fcvtzu v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT:    cmhi v2.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT:    bif v0.16b, v1.16b, v2.16b
+; CHECK-FP16-GI-NEXT:    xtn v0.2s, v0.2d
+; CHECK-FP16-GI-NEXT:    ret
 entry:
   %conv = fptoui <2 x double> %x to <2 x i64>
   %0 = icmp ult <2 x i64> %conv, <i64 4294967295, i64 4294967295>
@@ -39,11 +103,39 @@ entry:
 }
 
 define <2 x i32> @ustest_f64i32(<2 x double> %x) {
-; CHECK-LABEL: ustest_f64i32:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
-; CHECK-NEXT:    sqxtun v0.2s, v0.2d
-; CHECK-NEXT:    ret
+; CHECK-CVT-SD-LABEL: ustest_f64i32:
+; CHECK-CVT-SD:       // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-CVT-SD-NEXT:    sqxtun v0.2s, v0.2d
+; CHECK-CVT-SD-NEXT:    ret
+;
+; CHECK-FP16-SD-LABEL: ustest_f64i32:
+; CHECK-FP16-SD:       // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-FP16-SD-NEXT:    sqxtun v0.2s, v0.2d
+; CHECK-FP16-SD-NEXT:    ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f64i32:
+; CHECK-CVT-GI:       // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-CVT-GI-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT:    cmgt v2.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT:    bif v0.16b, v1.16b, v2.16b
+; CHECK-CVT-GI-NEXT:    cmgt v1.2d, v0.2d, #0
+; CHECK-CVT-GI-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-CVT-GI-NEXT:    xtn v0.2s, v0.2d
+; CHECK-CVT-GI-NEXT:    ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f64i32:
+; CHECK-FP16-GI:       // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-FP16-GI-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT:    cmgt v2.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT:    bif v0.16b, v1.16b, v2.16b
+; CHECK-FP16-GI-NEXT:    cmgt v1.2d, v0.2d, #0
+; CHECK-FP16-GI-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-FP16-GI-NEXT:    xtn v0.2s, v0.2d
+; CHECK-FP16-GI-NEXT:    ret
 entry:
   %conv = fptosi <2 x double> %x to <2 x i64>
   %0 = icmp slt <2 x i64> %conv, <i64 4294967295, i64 4294967295>
@@ -55,10 +147,57 @@ entry:
 }
 
 define <4 x i32> @stest_f32i32(<4 x float> %x) {
-; CHECK-LABEL: stest_f32i32:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
-; CHECK-NEXT:    ret
+; CHECK-CVT-SD-LABEL: stest_f32i32:
+; CHECK-CVT-SD:       // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT:    fcvtzs v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT:    ret
+;
+; CHECK-FP16-SD-LABEL: stest_f32i32:
+; CHECK-FP16-SD:       // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT:    fcvtzs v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT:    ret
+;
+; CHECK-CVT-GI-LABEL: stest_f32i32:
+; CHECK-CVT-GI:       // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT:    fcvtl v1.2d, v0.2s
+; CHECK-CVT-GI-NEXT:    fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT:    adrp x8, .LCPI3_1
+; CHECK-CVT-GI-NEXT:    ldr q2, [x8, :lo12:.LCPI3_1]
+; CHECK-CVT-GI-NEXT:    adrp x8, .LCPI3_0
+; CHECK-CVT-GI-NEXT:    fcvtzs v1.2d, v1.2d
+; CHECK-CVT-GI-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT:    cmgt v3.2d, v2.2d, v1.2d
+; CHECK-CVT-GI-NEXT:    cmgt v4.2d, v2.2d, v0.2d
+; CHECK-CVT-GI-NEXT:    bif v1.16b, v2.16b, v3.16b
+; CHECK-CVT-GI-NEXT:    bif v0.16b, v2.16b, v4.16b
+; CHECK-CVT-GI-NEXT:    ldr q2, [x8, :lo12:.LCPI3_0]
+; CHECK-CVT-GI-NEXT:    cmgt v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT:    cmgt v4.2d, v0.2d, v2.2d
+; CHECK-CVT-GI-NEXT:    bif v1.16b, v2.16b, v3.16b
+; CHECK-CVT-GI-NEXT:    bif v0.16b, v2.16b, v4.16b
+; CHECK-CVT-GI-NEXT:    uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-CVT-GI-NEXT:    ret
+;
+; CHECK-FP16-GI-LABEL: stest_f32i32:
+; CHECK-FP16-GI:       // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT:    fcvtl v1.2d, v0.2s
+; CHECK-FP16-GI-NEXT:    fcvtl2 v0.2d, v0.4s
+; CHECK-FP16-GI-NEXT:    adrp x8, .LCPI3_1
+; CHECK-FP16-GI-NEXT:    ldr q2, [x8, :lo12:.LCPI3_1]
+; CHECK-FP16-GI-NEXT:    adrp x8, .LCPI3_0
+; CHECK-FP16-GI-NEXT:    fcvtzs v1.2d, v1.2d
+; CHECK-FP16-GI-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT:    cmgt v3.2d, v2.2d, v1.2d
+; CHECK-FP16-GI-NEXT:    cmgt v4.2d, v2.2d, v0.2d
+; CHECK-FP16-GI-NEXT:    bif v1.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT:    bif v0.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT:    ldr q2, [x8, :lo12:.LCPI3_0]
+; CHECK-FP16-GI-NEXT:    cmgt v3.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT:    cmgt v4.2d, v0.2d, v2.2d
+; CHECK-FP16-GI-NEXT:    bif v1.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT:    bif v0.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT:    uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-FP16-GI-NEXT:    ret
 entry:
   %conv = fptosi <4 x float> %x to <4 x i64>
   %0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
@@ -70,10 +209,43 @@ entry:
 }
 
 define <4 x i32> @utest_f32i32(<4 x float> %x) {
-; CHECK-LABEL: utest_f32i32:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
-; CHECK-NEXT:    ret
+; CHECK-CVT-SD-LABEL: utest_f32i32:
+; CHECK-CVT-SD:       // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT:    ret
+;
+; CHECK-FP16-SD-LABEL: utest_f32i32:
+; CHECK-FP16-SD:       // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT:    ret
+;
+; CHECK-CVT-GI-LABEL: utest_f32i32:
+; CHECK-CVT-GI:       // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT:    fcvtl v2.2d, v0.2s
+; CHECK-CVT-GI-NEXT:    fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-CVT-GI-NEXT:    fcvtzu v2.2d, v2.2d
+; CHECK-CVT-GI-NEXT:    fcvtzu v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT:    cmhi v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT:    cmhi v4.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT:    bif v2.16b, v1.16b, v3.16b
+; CHECK-CVT-GI-NEXT:    bif v0.16b, v1.16b, v4.16b
+; CHECK-CVT-GI-NEXT:    uzp1 v0.4s, v2.4s, v0.4s
+; CHECK-CVT-GI-NEXT:    ret
+;
+; CHECK-FP16-GI-LABEL: utest_f32i32:
+; CHECK-FP16-GI:       // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT:    fcvtl v2.2d, v0.2s
+; CHECK-FP16-GI-NEXT:    fcvtl2 v0.2d, v0.4s
+; CHECK-FP16-GI-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-FP16-GI-NEXT:    fcvtzu v2.2d, v2.2d
+; CHECK-FP16-GI-NEXT:    fcvtzu v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT:    cmhi v3.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT:    cmhi v4.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT:    bif v2.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT:    bif v0.16b, v1.16b, v4.16b
+; CHECK-FP16-GI-NEXT:    uzp1 v0.4s, v2.4s, v0.4s
+; CHECK-FP16-GI-NEXT:    ret
 entry:
   %conv = fptoui <4 x float> %x to <4 x i64>
   %0 = icmp ult <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
@@ -83,10 +255,51 @@ entry:
 }
 
 define <4 x i32> @ustest_f32i32(<4 x float> %x) {
-; CHECK-LABEL: ustest_f32i32:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
-; CHECK-NEXT:    ret
+; CHECK-CVT-SD-LABEL: ustest_f32i32:
+; CHECK-CVT-SD:       // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT:    ret
+;
+; CHECK-FP16-SD-LABEL: ustest_f32i32:
+; CHECK-FP16-SD:       // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT:    ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f32i32:
+; CHECK-CVT-GI:       // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT:    fcvtl v2.2d, v0.2s
+; CHECK-CVT-GI-NEXT:    fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-CVT-GI-NEXT:    fcvtzs v2.2d, v2.2d
+; CHECK-CVT-GI-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT:    cmgt v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT:    cmgt v4.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT:    bif v2.16b, v1.16b, v3.16b
+; CHECK-CVT-GI-NEXT:    bif v0.16b, v1.16b, v4.16b
+; CHECK-CVT-GI-NEXT:    cmgt v1.2d, v2.2d, #0
+; CHECK-CVT-GI-NEXT:    cmgt v3.2d, v0.2d, #0
+; CHECK-CVT-GI-NEXT:    and v1.16b, v2.16b, v1.16b
+; CHECK-CVT-GI-NEXT:    and v0.16b, v0.16b, v3.16b
+; CHECK-CVT-GI-NEXT:    uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-CVT-GI-NEXT:    ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f32i32:
+; CHECK-FP16-GI:       // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT:    fcvtl v2.2d, v0.2s
+; CHECK-FP16-GI-NEXT:    fcvtl2 v0.2d, v0.4s
+; CHECK-FP16-GI-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-FP16-GI-NEXT:    fcvtzs v2.2d, v2.2d
+; CHECK-FP16-GI-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT:    cmgt v3.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT:    cmgt v4.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT:    bif v2.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT:    bif v0.16b, v1.16b, v4.16b
+; CHECK-FP16-GI-NEXT:    cmgt v1.2d, v2.2d, #0
+; CHECK-FP16-GI-NEXT:    cmgt v3.2d, v0.2d, #0
+; CHECK-FP16-GI-NEXT:    and v1.16b, v2.16b, v1.16b
+; CHECK-FP16-GI-NEXT:    and v0.16b, v0.16b, v3.16b
+; CHECK-FP16-GI-NEXT:    uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-FP16-GI-NEXT:    ret
 entry:
   %conv = fptosi <4 x float> %x to <4 x i64>
   %0 = icmp slt <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
@@ -98,11 +311,68 @@ entry:
 }
 
 define <4 x i32> @stest_f16i32(<4 x half> %x) {
-; CHECK-LABEL: stest_f16i32:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fcvtl v0.4s, v0.4h
-; CHECK-NEXT:    fcvtzs v0.4s, v0.4s
-; CHECK-NEXT:    ret
+; CHECK-CVT-SD-LABEL: stest_f16i32:
+; CHECK-CVT-SD:       // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-CVT-SD-NEXT:    fcvtzs v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT:    ret
+;
+; CHECK-FP16-SD-LABEL: stest_f16i32:
+; CHECK-FP16-SD:       // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-FP16-SD-NEXT:    fcvtzs v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT:    ret
+;
+; CHECK-CVT-GI-LABEL: stest_f16i32:
+; CHECK-CVT-GI:       // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-CVT-GI-NEXT:    adrp x8, .LCPI6_1
+; CHECK-CVT-GI-NEXT:    ldr q2, [x8, :lo12:.LCPI6_1]
+; CHECK-CVT-GI-NEXT:    adrp x8, .LCPI6_0
+; CHECK-CVT-GI-NEXT:    fcvtl v1.2d, v0.2s
+; CHECK-CVT-GI-NEXT:    fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT:    fcvtzs v1.2d, v1.2d
+; CHECK-CVT-GI-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT:    cmgt v3.2d, v2.2d, v1.2d
+; CHECK-CVT-GI-NEXT:    cmgt v4.2d, v2.2d, v0.2d
+; CHECK-CVT-GI-NEXT:    bif v1.16b, v2.16b, v3.16b
+; CHECK-CVT-GI-NEXT:    bif v0.16b, v2.16b, v4.16b
+; CHECK-CVT-GI-NEXT:    ldr q2, [x8, :lo12:.LCPI6_0]
+; CHECK-CVT-GI-NEXT:    cmgt v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT:    cmgt v4.2d, v0.2d, v2.2d
+; CHECK-CVT-GI-NEXT:    bif v1.16b, v2.16b, v3.16b
+; CHECK-CVT-GI-NEXT:    bif v0.16b, v2.16b, v4.16b
+; CHECK-CVT-GI-NEXT:    uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-CVT-GI-NEXT:    ret
+;
+; CHECK-FP16-GI-LABEL: stest_f16i32:
+; CHECK-FP16-GI:       // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT:    mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT:    mov h2, v0.h[2]
+; CHECK-FP16-GI-NEXT:    adrp x8, .LCPI6_1
+; CHECK-FP16-GI-NEXT:    mov h3, v0.h[3]
+; CHECK-FP16-GI-NEXT:    fcvt d0, h0
+; CHECK-FP16-GI-NEXT:    fcvt d1, h1
+; CHECK-FP16-GI-NEXT:    fcvt d2, h2
+; CHECK-FP16-GI-NEXT:    fcvt d3, h3
+; CHECK-FP16-GI-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-FP16-GI-NEXT:    mov v2.d[1], v3.d[0]
+; CHECK-FP16-GI-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT:    fcvtzs v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT:    ldr q2, [x8, :lo12:.LCPI6_1]
+; CHECK-FP16-GI-NEXT:    adrp x8, .LCPI6_0
+; CHECK-FP16-GI-NEXT:    cmgt v3.2d, v2.2d, v0.2d
+; CHECK-FP16-GI-NEXT:    cmgt v4.2d, v2.2d, v1.2d
+; CHECK-FP16-GI-NEXT:    bif v0.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT:    bif v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT:    ldr q2, [x8, :lo12:.LCPI6_0]
+; CHECK-FP16-GI-NEXT:    cmgt v3.2d, v0.2d, v2.2d
+; CHECK-FP16-GI-NEXT:    cmgt v4.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT:    bif v0.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT:    bif v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT:    uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT:    ret
 entry:
   %conv = fptosi <4 x half> %x to <4 x i64>
   %0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
@@ -114,11 +384,54 @@ entry:
 }
 
 define <4 x i32> @utesth_f16i32(<4 x half> %x) {
-; CHECK-LABEL: utesth_f16i32:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fcvtl v0.4s, v0.4h
-; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
-; CHECK-NEXT:    ret
+; CHECK-CVT-SD-LABEL: utesth_f16i32:
+; CHECK-CVT-SD:       // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-CVT-SD-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT:    ret
+;
+; CHECK-FP16-SD-LABEL: utesth_f16i32:
+; CHECK-FP16-SD:       // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-FP16-SD-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT:    ret
+;
+; CHECK-CVT-GI-LABEL: utesth_f16i32:
+; CHECK-CVT-GI:       // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-CVT-GI-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-CVT-GI-NEXT:    fcvtl v2.2d, v0.2s
+; CHECK-CVT-GI-NEXT:    fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT:    fcvtzu v2.2d, v2.2d
+; CHECK-CVT-GI-NEXT:    fcvtzu v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT:    cmhi v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT:    cmhi v4.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT:    bif v2.16b, v1.16b, v3.16b
+; CHECK-CVT-GI-NEXT:    bif v0.16b, v1.16b, v4.16b
+; CHECK-CVT-GI-NEXT:    uzp1 v0.4s, v2.4s, v0.4s
+; CHECK-CVT-GI-NEXT:    ret
+;
+; CHECK-FP16-GI-LABEL: utesth_f16i32:
+; CHECK-FP16-GI:       // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT:    mov h2, v0.h[1]
+; CHECK-FP16-GI-NEXT:    mov h3, v0.h[2]
+; CHECK-FP16-GI-NEXT:    mov h4, v0.h[3]
+; CHECK-FP16-GI-NEXT:    fcvt d0, h0
+; CHECK-FP16-GI-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-FP16-GI-NEXT:    fcvt d2, h2
+; CHECK-FP16-GI-NEXT:    fcvt d3, h3
+; CHECK-FP16-GI-NEXT:    fcvt d4, h4
+; CHECK-FP16-GI-NEXT:    mov v0.d[1], v2.d[0]
+; CHECK-FP16-GI-NEXT:    mov v3.d[1], v4.d[0]
+; CHECK-FP16-GI-NEXT:    fcvtzu v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT:    fcvtzu v2.2d, v3.2d
+; CHECK-FP16-GI-NEXT:    cmhi v3.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT:    cmhi v4.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT:    bif v0.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT:    bit v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT:    uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT:    ret
 entry:
   %conv = fptoui <4 x half> %x to <4 x i64>
   %0 = icmp ult <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
@@ -128,11 +441,62 @@ entry:
 }
 
 define <4 x i32> @ustest_f16i32(<4 x half> %x) {
-; CHECK-LABEL: ustest_f16i32:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    fcvtl v0.4s, v0.4h
-; CHECK-NEXT:    fcvtzu v0.4s, v0.4s
-; CHECK-NEXT:    ret
+; CHECK-CVT-SD-LABEL: ustest_f16i32:
+; CHECK-CVT-SD:       // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-CVT-SD-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT:    ret
+;
+; CHECK-FP16-SD-LABEL: ustest_f16i32:
+; CHECK-FP16-SD:       // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-FP16-SD-NEXT:    fcvtzu v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT:    ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f16i32:
+; CHECK-CVT-GI:       // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT:    fcvtl v0.4s, v0.4h
+; CHECK-CVT-GI-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-CVT-GI-NEXT:    fcvtl v2.2d, v0.2s
+; CHECK-CVT-GI-NEXT:    fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT:    fcvtzs v2.2d, v2.2d
+; CHECK-CVT-GI-NEXT:    fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT:    cmgt v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT:    cmgt v4.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT:    bif v2.16b, v1.16b, v3.16b
+; CHECK-CVT-GI-NEXT:    bif v0.16b, v1.16b, v4.16b
+; CHECK-CVT-GI-NEXT:    cmgt v1.2d, v2.2d, #0
+; CHECK-CVT-GI-NEXT:    cmgt v3.2d, v0.2d, #0
+; CHECK-CVT-GI-NEXT:    and v1.16b, v2.16b, v1.16b
+; CHECK-CVT-GI-NEXT:    and v0.16b, v0.16b, v3.16b
+; CHECK-CVT-GI-NEXT:    uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-CVT-GI-NEXT:    ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f16i32:
+; CHECK...
[truncated]

@jyli0116 jyli0116 requested a review from davemgreen August 19, 2025 13:35
davemgreen
davemgreen approved these changes Aug 19, 2025
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LGTM

@jyli0116 jyli0116 merged commit 5868580 into llvm:main Aug 19, 2025
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@jyli0116 jyli0116 deleted the GISel_truncsat_test branch August 20, 2025 08:58
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