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[PowerPC] Support -fpatchable-function-entry on PPC64LE #151569

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[PowerPC] Support -fpatchable-function-entry on PPC64LE #151569

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2 changes: 1 addition & 1 deletion clang/include/clang/Basic/Attr.td
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Original file line number Diff line number Diff line change
Expand Up @@ -954,7 +954,7 @@ def PatchableFunctionEntry
: InheritableAttr,
TargetSpecificAttr<TargetArch<
["aarch64", "aarch64_be", "loongarch32", "loongarch64", "riscv32",
"riscv64", "x86", "x86_64", "ppc", "ppc64"]>> {
"riscv64", "x86", "x86_64", "ppc", "ppc64", "ppc64le"]>> {
let Spellings = [GCC<"patchable_function_entry">];
let Subjects = SubjectList<[Function, ObjCMethod]>;
let Args = [UnsignedArgument<"Count">, DefaultIntArgument<"Offset", 0>,
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2 changes: 1 addition & 1 deletion clang/include/clang/Basic/AttrDocs.td
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Expand Up @@ -6567,7 +6567,7 @@ if omitted.``Section`` defaults to the ``-fpatchable-function-entry`` section n
set, or to ``__patchable_function_entries`` otherwise.

This attribute is only supported on
aarch64/aarch64-be/loongarch32/loongarch64/riscv32/riscv64/i386/x86-64/ppc/ppc64 targets.
aarch64/aarch64-be/loongarch32/loongarch64/riscv32/riscv64/i386/x86-64/ppc/ppc64/ppc64le targets.
For ppc/ppc64 targets, AIX is still not supported.
}];
}
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3 changes: 2 additions & 1 deletion clang/lib/Driver/ToolChains/Clang.cpp
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Expand Up @@ -6744,7 +6744,8 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
if (!Triple.isAArch64() && !Triple.isLoongArch() && !Triple.isRISCV() &&
!Triple.isX86() &&
!(!Triple.isOSAIX() && (Triple.getArch() == llvm::Triple::ppc ||
Triple.getArch() == llvm::Triple::ppc64)))
Triple.getArch() == llvm::Triple::ppc64 ||
Triple.getArch() == llvm::Triple::ppc64le)))
D.Diag(diag::err_drv_unsupported_opt_for_target)
<< A->getAsString(Args) << TripleStr;
else if (S.consumeInteger(10, Size) ||
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1 change: 1 addition & 0 deletions clang/test/Driver/fpatchable-function-entry.c
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Expand Up @@ -8,6 +8,7 @@
// RUN: %clang --target=riscv64 %s -fpatchable-function-entry=1,0 -c -### 2>&1 | FileCheck %s
// RUN: %clang --target=powerpc-unknown-linux-gnu %s -fpatchable-function-entry=1,0 -c -### 2>&1 | FileCheck %s
// RUN: %clang --target=powerpc64-unknown-linux-gnu %s -fpatchable-function-entry=1,0 -c -### 2>&1 | FileCheck %s
// RUN: %clang --target=powerpc64le-unknown-linux-gnu %s -fpatchable-function-entry=1,0 -c -### 2>&1 | FileCheck %s
// CHECK: "-fpatchable-function-entry=1"

// RUN: %clang --target=aarch64 -fsyntax-only %s -fpatchable-function-entry=1,1 -c -### 2>&1 | FileCheck --check-prefix=11 %s
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2 changes: 1 addition & 1 deletion clang/test/Sema/patchable-function-entry-attr.cpp
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Expand Up @@ -8,7 +8,7 @@
// RUN: %clang_cc1 -triple riscv64 -fsyntax-only -verify=silence %s
// RUN: %clang_cc1 -triple powerpc-unknown-linux-gnu -fsyntax-only -verify=silence %s
// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -fsyntax-only -verify=silence %s
// RUN: %clang_cc1 -triple ppc64le -fsyntax-only -verify %s
// RUN: %clang_cc1 -triple ppc64le -fsyntax-only -verify=silence %s
// RUN: %clang_cc1 -triple powerpc64-ibm-aix-xcoff -fsyntax-only -verify=AIX %s
// RUN: %clang_cc1 -triple powerpc-ibm-aix-xcoff -fsyntax-only -verify=AIX %s

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12 changes: 7 additions & 5 deletions llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
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Expand Up @@ -920,10 +920,6 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) {
case TargetOpcode::PATCHABLE_FUNCTION_ENTER: {
assert(!Subtarget->isAIXABI() &&
"AIX does not support patchable function entry!");
// PATCHABLE_FUNCTION_ENTER on little endian is for XRAY support which is
// handled in PPCLinuxAsmPrinter.
if (MAI->isLittleEndian())
return;
const Function &F = MF->getFunction();
unsigned Num = 0;
(void)F.getFnAttribute("patchable-function-entry")
Expand Down Expand Up @@ -1789,7 +1785,13 @@ void PPCLinuxAsmPrinter::emitInstruction(const MachineInstr *MI) {
// Update compiler-rt/lib/xray/xray_powerpc64.cc accordingly when number
// of instructions change.
// XRAY is only supported on PPC Linux little endian.
if (!MAI->isLittleEndian())
const Function &F = MF->getFunction();
unsigned Num = 0;
(void)F.getFnAttribute("patchable-function-entry")
.getValueAsString()
.getAsInteger(10, Num);

if (!MAI->isLittleEndian() || Num)
break;
MCSymbol *BeginOfSled = OutContext.createTempSymbol();
MCSymbol *EndOfSled = OutContext.createTempSymbol();
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49 changes: 49 additions & 0 deletions llvm/test/CodeGen/PowerPC/patchable-function-entry.ll
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Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
; RUN: llc -mtriple=powerpc %s -o - | FileCheck %s --check-prefixes=CHECK,PPC32
; RUN: llc -mtriple=powerpc64 %s -o - | FileCheck %s --check-prefixes=CHECK,PPC64
; RUN: llc -mtriple=powerpc64le %s -o - | FileCheck %s --check-prefix=PPC64LE

@a = global i32 0, align 4

Expand All @@ -9,6 +10,12 @@ define void @f0() {
; CHECK: # %bb.0:
; CHECK-NEXT: blr
; CHECK-NOT: .section __patchable_function_entries
;
; PPC64LE-LABEL: f0:
; PPC64LE-NOT: nop
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: blr
; PPC64LE-NOT: .section __patchable_function_entries
ret void
}

Expand All @@ -18,6 +25,22 @@ define void @f1() "patchable-function-entry"="0" {
; CHECK: # %bb.0:
; CHECK-NEXT: blr
; CHECK-NOT: .section __patchable_function_entries
;
; PPC64LE-LABEL: f1:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: .Ltmp0:
; PPC64LE-NEXT: b .Ltmp1
; PPC64LE-NEXT: nop
; PPC64LE-NEXT: std 0, -8(1)
; PPC64LE-NEXT: mflr 0
; PPC64LE-NEXT: bl __xray_FunctionEntry
; PPC64LE-NEXT: nop
; PPC64LE-NEXT: mtlr 0
; PPC64LE-NEXT: .Ltmp1:
; PPC64LE-NEXT: blr
; PPC64LE-NOT: .section __patchable_function_entries
; PPC64LE: .section xray_instr_map
; PPC64LE: .section xray_fn_idx
ret void
}

Expand All @@ -32,6 +55,17 @@ define void @f2() "patchable-function-entry"="1" {
; PPC64: .p2align 3, 0x0
; PPC32-NEXT: .long .Lfunc_begin2
; PPC64-NEXT: .quad .Lfunc_begin2
;
; PPC64LE-LABEL: f2:
; PPC64LE-LABEL-NEXT: .Lfunc_begin2:
; PPC64LE: # %bb.0:
; PPC64LE-NEXT: nop
; PPC64LE-NEXT: blr
; PPC64LE: .section __patchable_function_entries
; PPC64LE: .p2align 3, 0x0
; PPC64LE-NEXT: .quad .Lfunc_begin2
; PPC64LE-NOT: .section xray_instr_map
; PPC64LE-NOT: .section xray_fn_idx
ret void
}

Expand All @@ -52,6 +86,21 @@ define i32 @f3() "patchable-function-entry"="1" "patchable-function-prefix"="2"
; PPC64: .p2align 3, 0x0
; PPC32-NEXT: .long .Ltmp0
; PPC64-NEXT: .quad .Ltmp0
;
; PC64LE-LABEL: .Ltmp3:
; PC64LE-COUNT-2: nop
; PC64LE-LABEL: f3:
; PC64LE: # %bb.0:
; PC64LE-NEXT: nop
; PC64LE: addis 3, 2, .LC0@toc@ha
; PC64LE-NEXT: ld 3, .LC0@toc@l(3)
; PC64LE-NEXT: lwz 3, 0(3)
; PC64LE: blr
; PC64LE: .section __patchable_function_entries
; PPC64LE: .p2align 3, 0x0
; PPC64LE-NEXT: .quad .Ltmp3
; PC64LE-NOT: .section xray_instr_map
; PC64LE-NOT: .section xray_fn_idx
entry:
%0 = load i32, ptr @a, align 4
ret i32 %0
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