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[SelectionDAG] Add ISD::VSELECT to SelectionDAG::canCreateUndefOrPoison. #143760

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Jun 11, 2025
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[SelectionDAG] Add ISD::VSELECT to SelectionDAG::canCreateUndefOrPoison. #143760

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1 change: 1 addition & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Expand Up @@ -5553,6 +5553,7 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
case ISD::BUILD_VECTOR:
case ISD::BUILD_PAIR:
case ISD::SPLAT_VECTOR:
case ISD::VSELECT:
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Is it safe to also add normal SELECT as well then? Or are we afraid of possible fast-math-flags?

Maybe the early out above related to ConsiderFlags should be seen as taking care of any poison generating flags?

(I think ISDOpcodes.h is still lacking documentation about SELECT having flags, and possibly undefined results. And to be honest, I don't know myself if VSELECT can have fast-math flags as well. Not sure how developers are supposed to know such things if we do not document it in ISDOpcodes.h?)

Or are we perhaps afraid of performance penalties if making helpers like this more "complete" to cover all ISD nodes?

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I think it should be ok, I just assumed some number of tests would need to be updated and reviewed and I haven't tried yet. VSELECT happened to be what I was looking at the time.

return false;

case ISD::SELECT_CC:
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69 changes: 34 additions & 35 deletions llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
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Expand Up @@ -313,12 +313,12 @@ define i32 @test_nxv128i1(<vscale x 128 x i1> %x) {
; CHECK-NEXT: vslidedown.vx v0, v6, a0
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v6, v7, a1
; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v7, a0
; CHECK-NEXT: vslidedown.vx v5, v6, a0
; CHECK-NEXT: vslidedown.vx v4, v7, a0
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vmv1r.v v0, v4
; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
; CHECK-NEXT: vmv1r.v v0, v5
; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
Expand Down Expand Up @@ -364,9 +364,9 @@ define i32 @test_nxv256i1(<vscale x 256 x i1> %x) {
; CHECK-NEXT: vmv1r.v v7, v9
; CHECK-NEXT: vmv1r.v v5, v8
; CHECK-NEXT: vmv1r.v v4, v0
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmv.v.i v24, 0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
; CHECK-NEXT: vmerge.vim v8, v24, 1, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: mv a2, a0
Expand All @@ -376,7 +376,7 @@ define i32 @test_nxv256i1(<vscale x 256 x i1> %x) {
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmv1r.v v0, v5
; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
; CHECK-NEXT: vmerge.vim v8, v24, 1, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0
Expand All @@ -388,52 +388,52 @@ define i32 @test_nxv256i1(<vscale x 256 x i1> %x) {
; CHECK-NEXT: vslidedown.vx v3, v4, a0
; CHECK-NEXT: vslidedown.vx v2, v5, a0
; CHECK-NEXT: vmv.v.v v0, v3
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
; CHECK-NEXT: vmerge.vim v8, v24, 1, v0
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: mv a3, a2
; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vmv1r.v v0, v2
; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
; CHECK-NEXT: vmerge.vim v8, v24, 1, v0
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v3, a1
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
; CHECK-NEXT: vmerge.vim v8, v24, 1, v0
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v16, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v2, a1
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
; CHECK-NEXT: vmerge.vim v24, v8, 1, v0
; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v4, a1
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
; CHECK-NEXT: vmerge.vim v8, v24, 1, v0
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v5, a1
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, ma
; CHECK-NEXT: vmerge.vim v24, v24, 1, v0
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v6, a1
; CHECK-NEXT: vslidedown.vx v5, v7, a1
; CHECK-NEXT: vslidedown.vx v4, v6, a1
; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vmv1r.v v0, v4
; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
; CHECK-NEXT: vmv1r.v v0, v5
; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
; CHECK-NEXT: vadd.vv v8, v16, v8
; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v24
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
Expand All @@ -443,15 +443,15 @@ define i32 @test_nxv256i1(<vscale x 256 x i1> %x) {
; CHECK-NEXT: vslidedown.vx v0, v4, a1
; CHECK-NEXT: vslidedown.vx v3, v5, a1
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
; CHECK-NEXT: vmv1r.v v0, v3
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
; CHECK-NEXT: vadd.vv v8, v8, v24
; CHECK-NEXT: vadd.vv v8, v8, v16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
Expand Down Expand Up @@ -492,16 +492,16 @@ define i32 @test_nxv256i1(<vscale x 256 x i1> %x) {
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vadd.vi v24, v24, 1, v0.t
; CHECK-NEXT: vadd.vv v24, v24, v8
; CHECK-NEXT: vadd.vv v0, v24, v8
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vadd.vv v8, v8, v0
; CHECK-NEXT: vadd.vv v16, v24, v16
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; CHECK-NEXT: vadd.vv v8, v8, v24
; CHECK-NEXT: vadd.vv v16, v0, v16
; CHECK-NEXT: vadd.vv v8, v16, v8
; CHECK-NEXT: vmv.s.x v16, zero
; CHECK-NEXT: vredsum.vs v8, v8, v16
Expand Down Expand Up @@ -537,18 +537,17 @@ entry:
define i16 @test_narrow_nxv64i1(<vscale x 64 x i1> %x) {
; CHECK-LABEL: test_narrow_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v0, a0
; CHECK-NEXT: vslidedown.vx v0, v0, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vadd.vi v16, v16, 1, v0.t
; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: vredsum.vs v8, v16, v8
; CHECK-NEXT: vadd.vi v8, v8, 1, v0.t
; CHECK-NEXT: vmv.s.x v16, zero
; CHECK-NEXT: vredsum.vs v8, v8, v16
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
entry:
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
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Expand Up @@ -260,18 +260,18 @@ define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv64i1(<vscale x 64 x i1
; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; ZIP-NEXT: vmv1r.v v9, v0
; ZIP-NEXT: vmv1r.v v0, v8
; ZIP-NEXT: vmv.v.i v16, 0
; ZIP-NEXT: vmerge.vim v24, v16, 1, v0
; ZIP-NEXT: vmv.v.i v24, 0
; ZIP-NEXT: vmerge.vim v16, v24, 1, v0
; ZIP-NEXT: vmv1r.v v0, v9
; ZIP-NEXT: vmerge.vim v8, v16, 1, v0
; ZIP-NEXT: vmerge.vim v8, v24, 1, v0
; ZIP-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; ZIP-NEXT: ri.vzip2b.vv v4, v8, v24
; ZIP-NEXT: ri.vzip2b.vv v20, v12, v28
; ZIP-NEXT: ri.vzip2a.vv v0, v8, v24
; ZIP-NEXT: ri.vzip2a.vv v16, v12, v28
; ZIP-NEXT: ri.vzip2b.vv v4, v8, v16
; ZIP-NEXT: ri.vzip2b.vv v28, v12, v20
; ZIP-NEXT: ri.vzip2a.vv v0, v8, v16
; ZIP-NEXT: ri.vzip2a.vv v24, v12, v20
; ZIP-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; ZIP-NEXT: vmsne.vi v9, v0, 0
; ZIP-NEXT: vmsne.vi v8, v16, 0
; ZIP-NEXT: vmsne.vi v8, v24, 0
; ZIP-NEXT: vmv1r.v v0, v9
; ZIP-NEXT: ret
%res = call <vscale x 128 x i1> @llvm.vector.interleave2.nxv128i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b)
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/avx10_2_512bf16-arith.ll
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Expand Up @@ -94,8 +94,8 @@ define <32 x bfloat> @test_int_x86_avx10_maskz_sub_bf16_512(<32 x bfloat> %src,
;
; X86-LABEL: test_int_x86_avx10_maskz_sub_bf16_512:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08]
; X86-NEXT: kmovd {{[0-9]+}}(%esp), %k1 # encoding: [0xc4,0xe1,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08]
; X86-NEXT: vsubbf16 %zmm2, %zmm1, %zmm0 {%k1} {z} # encoding: [0x62,0xf5,0x75,0xc9,0x5c,0xc2]
; X86-NEXT: vsubbf16 (%eax), %zmm1, %zmm1 # encoding: [0x62,0xf5,0x75,0x48,0x5c,0x08]
; X86-NEXT: vsubbf16 %zmm1, %zmm0, %zmm0 {%k1} # encoding: [0x62,0xf5,0x7d,0x49,0x5c,0xc1]
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/avx10_2bf16-arith.ll
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Expand Up @@ -147,8 +147,8 @@ define <16 x bfloat> @test_int_x86_avx10_maskz_sub_bf16_256(<16 x bfloat> %src,
;
; X86-LABEL: test_int_x86_avx10_maskz_sub_bf16_256:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08]
; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08]
; X86-NEXT: vsubbf16 %ymm2, %ymm1, %ymm0 {%k1} {z} # encoding: [0x62,0xf5,0x75,0xa9,0x5c,0xc2]
; X86-NEXT: vsubbf16 (%eax), %ymm1, %ymm1 # encoding: [0x62,0xf5,0x75,0x28,0x5c,0x08]
; X86-NEXT: vsubbf16 %ymm1, %ymm0, %ymm0 {%k1} # encoding: [0x62,0xf5,0x7d,0x29,0x5c,0xc1]
Expand Down Expand Up @@ -201,8 +201,8 @@ define <8 x bfloat> @test_int_x86_avx10_maskz_sub_bf16_128(<8 x bfloat> %src, <8
;
; X86-LABEL: test_int_x86_avx10_maskz_sub_bf16_128:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08]
; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08]
; X86-NEXT: vsubbf16 %xmm2, %xmm1, %xmm0 {%k1} {z} # encoding: [0x62,0xf5,0x75,0x89,0x5c,0xc2]
; X86-NEXT: vsubbf16 (%eax), %xmm1, %xmm1 # encoding: [0x62,0xf5,0x75,0x08,0x5c,0x08]
; X86-NEXT: vsubbf16 %xmm1, %xmm0, %xmm0 {%k1} # encoding: [0x62,0xf5,0x7d,0x09,0x5c,0xc1]
Expand Down
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