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[test][AArch64] Adjust vector insertion lit tests #143101
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@llvm/pr-subscribers-backend-aarch64 Author: Björn Pettersson (bjope) ChangesThe test cases test_insert_v16i8_insert_2_undef_base and test_insert_v16i8_insert_2_undef_base_different_valeus in CodeGen/AArch64/arm64-vector-insertion.ll was leaving element 8 in the vector as "undef" without any real explanation. It kind of looked like a typo as the input IR looked like this This patch is cleaning up the tests a bit by adding separate test cases to validate what is happening when skipping insert at index 8, while amending the original tests cases to use %v.8 instead of %v.7 when creating %v.10. Full diff: https://github.com/llvm/llvm-project/pull/143101.diff 1 Files Affected:
diff --git a/llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll b/llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
index 94074d1689f6a..5962150ac9ffc 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
@@ -66,6 +66,35 @@ define <16 x i8> @test_insert_v16i8_insert_2_undef_base(i8 %a) {
%v.6 = insertelement <16 x i8> %v.4, i8 %a, i32 6
%v.7 = insertelement <16 x i8> %v.6, i8 %a, i32 7
%v.8 = insertelement <16 x i8> %v.7, i8 %a, i32 8
+ %v.10 = insertelement <16 x i8> %v.8, i8 %a, i32 10
+ %v.11 = insertelement <16 x i8> %v.10, i8 %a, i32 11
+ %v.12 = insertelement <16 x i8> %v.11, i8 %a, i32 12
+ %v.13 = insertelement <16 x i8> %v.12, i8 %a, i32 13
+ %v.14 = insertelement <16 x i8> %v.13, i8 %a, i32 14
+ %v.15 = insertelement <16 x i8> %v.14, i8 %a, i32 15
+ ret <16 x i8> %v.15
+}
+
+; Similar to above, but we leave element 8 as undef. One interesting part with
+; this test case is that %a may be poison, so simply inserting %a also at
+; index 8 would make the result vector more poisonous.
+define <16 x i8> @test_insert_v16i8_insert_2_undef_base_skip8(i32 %a0) {
+; CHECK-LABEL: test_insert_v16i8_insert_2_undef_base_skip8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: lsr w8, w0, #5
+; CHECK-NEXT: dup.16b v0, w8
+; CHECK-NEXT: mov.b v0[5], wzr
+; CHECK-NEXT: mov.b v0[9], wzr
+; CHECK-NEXT: ret
+ %a1 = lshr exact i32 %a0, 5
+ %a = trunc i32 %a1 to i8
+ %v.0 = insertelement <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef> , i8 %a, i32 0
+ %v.1 = insertelement <16 x i8> %v.0, i8 %a, i32 1
+ %v.2 = insertelement <16 x i8> %v.1, i8 %a, i32 2
+ %v.3 = insertelement <16 x i8> %v.2, i8 %a, i32 3
+ %v.4 = insertelement <16 x i8> %v.3, i8 %a, i32 4
+ %v.6 = insertelement <16 x i8> %v.4, i8 %a, i32 6
+ %v.7 = insertelement <16 x i8> %v.6, i8 %a, i32 7
%v.10 = insertelement <16 x i8> %v.7, i8 %a, i32 10
%v.11 = insertelement <16 x i8> %v.10, i8 %a, i32 11
%v.12 = insertelement <16 x i8> %v.11, i8 %a, i32 12
@@ -94,6 +123,42 @@ define <16 x i8> @test_insert_v16i8_insert_2_undef_base_different_valeus(i8 %a,
%v.6 = insertelement <16 x i8> %v.4, i8 %a, i32 6
%v.7 = insertelement <16 x i8> %v.6, i8 %b, i32 7
%v.8 = insertelement <16 x i8> %v.7, i8 %a, i32 8
+ %v.10 = insertelement <16 x i8> %v.8, i8 %a, i32 10
+ %v.11 = insertelement <16 x i8> %v.10, i8 %a, i32 11
+ %v.12 = insertelement <16 x i8> %v.11, i8 %b, i32 12
+ %v.13 = insertelement <16 x i8> %v.12, i8 %a, i32 13
+ %v.14 = insertelement <16 x i8> %v.13, i8 %a, i32 14
+ %v.15 = insertelement <16 x i8> %v.14, i8 %b, i32 15
+ ret <16 x i8> %v.15
+}
+
+; Similar to above, but we leave element 8 as undef. One interesting part with
+; this test case is that %a and %b may be poison, so simply inserting %a or %b
+; at index 8 would make the result vector more poisonous.
+define <16 x i8> @test_insert_v16i8_insert_2_undef_base_different_valeus_skip8(i32 %a0, i32 %b0) {
+; CHECK-LABEL: test_insert_v16i8_insert_2_undef_base_different_valeus_skip8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: lsr w8, w0, #5
+; CHECK-NEXT: dup.16b v0, w8
+; CHECK-NEXT: lsr w8, w1, #5
+; CHECK-NEXT: mov.b v0[2], w8
+; CHECK-NEXT: mov.b v0[5], wzr
+; CHECK-NEXT: mov.b v0[7], w8
+; CHECK-NEXT: mov.b v0[9], wzr
+; CHECK-NEXT: mov.b v0[12], w8
+; CHECK-NEXT: mov.b v0[15], w8
+; CHECK-NEXT: ret
+ %a1 = lshr exact i32 %a0, 5
+ %a = trunc i32 %a1 to i8
+ %b1 = lshr exact i32 %b0, 5
+ %b = trunc i32 %b1 to i8
+ %v.0 = insertelement <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef> , i8 %a, i32 0
+ %v.1 = insertelement <16 x i8> %v.0, i8 %a, i32 1
+ %v.2 = insertelement <16 x i8> %v.1, i8 %b, i32 2
+ %v.3 = insertelement <16 x i8> %v.2, i8 %a, i32 3
+ %v.4 = insertelement <16 x i8> %v.3, i8 %a, i32 4
+ %v.6 = insertelement <16 x i8> %v.4, i8 %a, i32 6
+ %v.7 = insertelement <16 x i8> %v.6, i8 %b, i32 7
%v.10 = insertelement <16 x i8> %v.7, i8 %a, i32 10
%v.11 = insertelement <16 x i8> %v.10, i8 %a, i32 11
%v.12 = insertelement <16 x i8> %v.11, i8 %b, i32 12
|
You can test this locally with the following command:git diff -U0 --pickaxe-regex -S '([^a-zA-Z0-9#_-]undef[^a-zA-Z0-9_-]|UndefValue::get)' 'HEAD~1' HEAD llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll The following files introduce new uses of undef:
Undef is now deprecated and should only be used in the rare cases where no replacement is possible. For example, a load of uninitialized memory yields In tests, avoid using For example, this is considered a bad practice: define void @fn() {
...
br i1 undef, ...
} Please use the following instead: define void @fn(i1 %cond) {
...
br i1 %cond, ...
} Please refer to the Undefined Behavior Manual for more information. |
The test cases test_insert_v16i8_insert_2_undef_base and test_insert_v16i8_insert_2_undef_base_different_valeus in CodeGen/AArch64/arm64-vector-insertion.ll was leaving element 8 in the vector as "undef" without any real explanation. It kind of looked like a typo as the input IR looked like this %v.8 = insertelement <16 x i8> %v.7, i8 %a, i32 8 %v.10 = insertelement <16 x i8> %v.7, i8 %a, i32 10 leaving %v.8 as unused. This patch is cleaning up the tests a bit by adding separate test cases to validate what is happening when skipping insert at index 8, while amending the original tests cases to use %v.8 instead of %v.7 when creating %v.10.
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The test cases test_insert_v16i8_insert_2_undef_base and test_insert_v16i8_insert_2_undef_base_different_valeus in CodeGen/AArch64/arm64-vector-insertion.ll was leaving element 8 in the vector as "undef" without any real explanation. It kind of looked like a typo as the input IR looked like this %v.8 = insertelement <16 x i8> %v.7, i8 %a, i32 8 %v.10 = insertelement <16 x i8> %v.7, i8 %a, i32 10 leaving %v.8 as unused. This patch is cleaning up the tests a bit by adding separate test cases to validate what is happening when skipping insert at index 8, while amending the original tests cases to use %v.8 instead of %v.7 when creating %v.10.
The test cases test_insert_v16i8_insert_2_undef_base and test_insert_v16i8_insert_2_undef_base_different_valeus in CodeGen/AArch64/arm64-vector-insertion.ll was leaving element 8 in the vector as "undef" without any real explanation. It kind of looked like a typo as the input IR looked like this %v.8 = insertelement <16 x i8> %v.7, i8 %a, i32 8 %v.10 = insertelement <16 x i8> %v.7, i8 %a, i32 10 leaving %v.8 as unused. This patch is cleaning up the tests a bit by adding separate test cases to validate what is happening when skipping insert at index 8, while amending the original tests cases to use %v.8 instead of %v.7 when creating %v.10.
The test cases test_insert_v16i8_insert_2_undef_base and test_insert_v16i8_insert_2_undef_base_different_valeus in CodeGen/AArch64/arm64-vector-insertion.ll was leaving element 8 in the vector as "undef" without any real explanation. It kind of looked like a typo as the input IR looked like this %v.8 = insertelement <16 x i8> %v.7, i8 %a, i32 8 %v.10 = insertelement <16 x i8> %v.7, i8 %a, i32 10 leaving %v.8 as unused. This patch is cleaning up the tests a bit by adding separate test cases to validate what is happening when skipping insert at index 8, while amending the original tests cases to use %v.8 instead of %v.7 when creating %v.10.
The test cases test_insert_v16i8_insert_2_undef_base and test_insert_v16i8_insert_2_undef_base_different_valeus in CodeGen/AArch64/arm64-vector-insertion.ll was leaving element 8 in the vector as "undef" without any real explanation. It kind of looked like a typo as the input IR looked like this
%v.8 = insertelement <16 x i8> %v.7, i8 %a, i32 8
%v.10 = insertelement <16 x i8> %v.7, i8 %a, i32 10
leaving %v.8 as unused.
This patch is cleaning up the tests a bit by adding separate test cases to validate what is happening when skipping insert at index 8, while amending the original tests cases to use %v.8 instead of %v.7 when creating %v.10.