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[RISCV] Select unsigned bitfield insert for XAndesPerf #142737

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Merged
merged 4 commits into from
Jun 6, 2025
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[RISCV] Select unsigned bitfield insert for XAndesPerf #142737

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4d5c0f4
[RISCV] Pre-commit
tclin914 Jun 3, 2025
27d670f
[RISCV] Select unsigned bitfield insert for XAndesPerf
tclin914 Jun 3, 2025
de9c8ce
Make the lsb/msb arguments/variables to truly be least significant bit
tclin914 Jun 5, 2025
1c38d74
Move the selection of 0 into `tryUnsignedBitfieldInsertInZero`
tclin914 Jun 5, 2025
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33 changes: 33 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -688,6 +688,26 @@ bool RISCVDAGToDAGISel::tryUnsignedBitfieldExtract(SDNode *Node, SDLoc DL,
return true;
}

bool RISCVDAGToDAGISel::tryUnsignedBitfieldInsertInZero(SDNode *Node, SDLoc DL,
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I think we can just inline this.

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I would prefer not. It's good to name it, and it provides a single place for other vendors to add their logic for their instructions here.

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@topperc topperc Jun 4, 2025 •
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If we keep it, I would like the lsb/msb arguments to truly be least significant bit and most significant bit of the insertion. The encoding tricks used by the Andes instruction should be done inside the function.

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Agree with @lenary's point and have updated the lsb/msb arguments/variables to accurately represent the least significant bit and most significant bit of the insertion.

MVT VT, SDValue X,
unsigned Msb,
unsigned Lsb) {
// Only supported with XAndesPerf at the moment.
if (!Subtarget->hasVendorXAndesPerf())
return false;

unsigned Opc = RISCV::NDS_BFOZ;

// If the Lsb is equal to the Msb, then the Lsb should be 0.
if (Lsb == Msb)
Lsb = 0;
SDNode *Ubi = CurDAG->getMachineNode(Opc, DL, VT, X,
CurDAG->getTargetConstant(Lsb, DL, VT),
CurDAG->getTargetConstant(Msb, DL, VT));
ReplaceNode(Node, Ubi);
return true;
}

bool RISCVDAGToDAGISel::tryIndexedLoad(SDNode *Node) {
// Target does not support indexed loads.
if (!Subtarget->hasVendorXTHeadMemIdx())
Expand Down Expand Up @@ -1324,6 +1344,19 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
return;
}

// Try to use an unsigned bitfield insert (e.g., nds.bfoz) if
// available.
// Transform (and (shl x, c2), c1)
// -> (<bfinsert> x, msb, lsb)
// e.g.
// (and (shl x, 12), 0x00fff000)
// If XLen = 32 and C2 = 12, then
// Msb = 32 - 8 - 1 = 23 and Lsb = 12
const unsigned Msb = XLen - Leading - 1;
const unsigned Lsb = C2;
if (tryUnsignedBitfieldInsertInZero(Node, DL, VT, X, Msb, Lsb))
return;

// (srli (slli c2+c3), c3)
if (OneUseOrZExtW && !IsCANDI) {
SDNode *SLLI = CurDAG->getMachineNode(
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
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Original file line number Diff line number Diff line change
Expand Up @@ -79,6 +79,8 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
bool trySignedBitfieldExtract(SDNode *Node);
bool tryUnsignedBitfieldExtract(SDNode *Node, SDLoc DL, MVT VT, SDValue X,
unsigned Msb, unsigned Lsb);
bool tryUnsignedBitfieldInsertInZero(SDNode *Node, SDLoc DL, MVT VT,
SDValue X, unsigned Msb, unsigned Lsb);
bool tryIndexedLoad(SDNode *Node);

bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
Expand Down
52 changes: 52 additions & 0 deletions llvm/test/CodeGen/RISCV/rv32xandesperf.ll
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Expand Up @@ -2,6 +2,10 @@
; RUN: llc -O0 -mtriple=riscv32 -mattr=+xandesperf -verify-machineinstrs < %s \
; RUN: | FileCheck %s

; NDS.BFOZ

; MSB >= LSB

define i32 @bfoz_from_and_i32(i32 %x) {
; CHECK-LABEL: bfoz_from_and_i32:
; CHECK: # %bb.0:
Expand Down Expand Up @@ -70,6 +74,54 @@ define i64 @bfoz_from_lshr_and_i64(i64 %x) {
ret i64 %shifted
}

; MSB = 0

define i32 @bfoz_from_and_shl_with_msb_zero_i32(i32 %x) {
; CHECK-LABEL: bfoz_from_and_shl_with_msb_zero_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.bfoz a0, a0, 0, 15
; CHECK-NEXT: ret
%shifted = shl i32 %x, 15
%masked = and i32 %shifted, 32768
ret i32 %masked
}

define i32 @bfoz_from_lshr_shl_with_msb_zero_i32(i32 %x) {
; CHECK-LABEL: bfoz_from_lshr_shl_with_msb_zero_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.bfoz a0, a0, 0, 18
; CHECK-NEXT: ret
%shl = shl i32 %x, 31
%lshr = lshr i32 %shl, 13
ret i32 %lshr
}

; MSB < LSB

define i32 @bfoz_from_and_shl_i32(i32 %x) {
; CHECK-LABEL: bfoz_from_and_shl_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.bfoz a0, a0, 12, 23
; CHECK-NEXT: ret
%shifted = shl i32 %x, 12
%masked = and i32 %shifted, 16773120
ret i32 %masked
}

define i32 @bfoz_from_lshr_shl_i32(i32 %x) {
; CHECK-LABEL: bfoz_from_lshr_shl_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.bfoz a0, a0, 19, 24
; CHECK-NEXT: ret
%shl = shl i32 %x, 26
%lshr = lshr i32 %shl, 7
ret i32 %lshr
}

; NDS.BFOS

; MSB >= LSB

define i32 @bfos_from_ashr_shl_i32(i32 %x) {
; CHECK-LABEL: bfos_from_ashr_shl_i32:
; CHECK: # %bb.0:
Expand Down
92 changes: 92 additions & 0 deletions llvm/test/CodeGen/RISCV/rv64xandesperf.ll
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Expand Up @@ -2,6 +2,10 @@
; RUN: llc -mtriple=riscv64 -mattr=+xandesperf -verify-machineinstrs < %s \
; RUN: | FileCheck %s

; NDS.BFOZ

; MSB >= LSB

define i32 @bfoz_from_and_i32(i32 %x) {
; CHECK-LABEL: bfoz_from_and_i32:
; CHECK: # %bb.0:
Expand Down Expand Up @@ -60,6 +64,94 @@ define i64 @bfoz_from_lshr_and_i64(i64 %x) {
ret i64 %shifted
}

; MSB = 0

define i32 @bfoz_from_and_shl_with_msb_zero_i32(i32 %x) {
; CHECK-LABEL: bfoz_from_and_shl_with_msb_zero_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.bfoz a0, a0, 0, 15
; CHECK-NEXT: ret
%shifted = shl i32 %x, 15
%masked = and i32 %shifted, 32768
ret i32 %masked
}

define i64 @bfoz_from_and_shl_with_msb_zero_i64(i64 %x) {
; CHECK-LABEL: bfoz_from_and_shl_with_msb_zero_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.bfoz a0, a0, 0, 48
; CHECK-NEXT: ret
%shifted = shl i64 %x, 48
%masked = and i64 %shifted, 281474976710656
ret i64 %masked
}

define i32 @bfoz_from_lshr_shl_with_msb_zero_i32(i32 %x) {
; CHECK-LABEL: bfoz_from_lshr_shl_with_msb_zero_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.bfoz a0, a0, 0, 18
; CHECK-NEXT: ret
%shl = shl i32 %x, 31
%lshr = lshr i32 %shl, 13
ret i32 %lshr
}

define i64 @bfoz_from_lshr_shl_with_msb_zero_i64(i64 %x) {
; CHECK-LABEL: bfoz_from_lshr_shl_with_msb_zero_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.bfoz a0, a0, 0, 44
; CHECK-NEXT: ret
%shl = shl i64 %x, 63
%lshr = lshr i64 %shl, 19
ret i64 %lshr
}

; MSB < LSB

define i32 @bfoz_from_and_shl_i32(i32 %x) {
; CHECK-LABEL: bfoz_from_and_shl_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.bfoz a0, a0, 12, 23
; CHECK-NEXT: ret
%shifted = shl i32 %x, 12
%masked = and i32 %shifted, 16773120
ret i32 %masked
}

define i64 @bfoz_from_and_shl_i64(i64 %x) {
; CHECK-LABEL: bfoz_from_and_shl_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.bfoz a0, a0, 24, 35
; CHECK-NEXT: ret
%shifted = shl i64 %x, 24
%masked = and i64 %shifted, 68702699520
ret i64 %masked
}

define i32 @bfoz_from_lshr_shl_i32(i32 %x) {
; CHECK-LABEL: bfoz_from_lshr_shl_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.bfoz a0, a0, 19, 24
; CHECK-NEXT: ret
%shl = shl i32 %x, 26
%lshr = lshr i32 %shl, 7
ret i32 %lshr
}

define i64 @bfoz_from_lshr_shl_i64(i64 %x) {
; CHECK-LABEL: bfoz_from_lshr_shl_i64:
; CHECK: # %bb.0:
; CHECK-NEXT: nds.bfoz a0, a0, 25, 48
; CHECK-NEXT: ret
%shl = shl i64 %x, 40
%lshr = lshr i64 %shl, 15
ret i64 %lshr
}

; NDS.BFOS

; MSB >= LSB

define i32 @bfos_from_ashr_shl_i32(i32 %x) {
; CHECK-LABEL: bfos_from_ashr_shl_i32:
; CHECK: # %bb.0:
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/RISCV/rv64zba.ll
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Expand Up @@ -24,8 +24,7 @@ define i64 @slliuw(i64 %a) nounwind {
;
; RV64XANDESPERF-LABEL: slliuw:
; RV64XANDESPERF: # %bb.0:
; RV64XANDESPERF-NEXT: slli a0, a0, 32
; RV64XANDESPERF-NEXT: srli a0, a0, 31
; RV64XANDESPERF-NEXT: nds.bfoz a0, a0, 1, 32
; RV64XANDESPERF-NEXT: ret
%conv1 = shl i64 %a, 1
%shl = and i64 %conv1, 8589934590
Expand Down