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[AArch64][SVE] Improve fixed-length addressing modes. #129732

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Merged
merged 8 commits into from
Mar 6, 2025
Merged

[AArch64][SVE] Improve fixed-length addressing modes. #129732

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624d1e9
Precommit tests
rj-jesus Mar 4, 2025
85921fc
[AArch64][SVE] Improve VLS imm addressing modes.
rj-jesus Mar 4, 2025
7ea47e5
Add unpacked/overpacked tests and move up VScale
rj-jesus Mar 4, 2025
25cee06
Add braces around if
rj-jesus Mar 5, 2025
07d5584
Change MulImm to std::optional<int64_t> (NFC)
rj-jesus Mar 5, 2025
2becfc6
Revert "Change MulImm to std::optional<int64_t> (NFC)"
rj-jesus Mar 5, 2025
9329a30
Add getSVEVectorSizeInBits to query known SVE length
rj-jesus Mar 5, 2025
c3ee9c7
Remove assert and redundant check
rj-jesus Mar 5, 2025
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9 changes: 3 additions & 6 deletions clang/test/CodeGen/AArch64/sve-vector-bits-codegen.c
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Original file line number Diff line number Diff line change
Expand Up @@ -13,12 +13,9 @@

void func(int *restrict a, int *restrict b) {
// CHECK-LABEL: func
// CHECK256-COUNT-1: str
// CHECK256-COUNT-7: st1w
// CHECK512-COUNT-1: str
// CHECK512-COUNT-3: st1w
// CHECK1024-COUNT-1: str
// CHECK1024-COUNT-1: st1w
// CHECK256-COUNT-8: str
// CHECK512-COUNT-4: str
// CHECK1024-COUNT-2: str
// CHECK2048-COUNT-1: st1w
#pragma clang loop vectorize(enable)
for (int i = 0; i < 64; ++i)
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19 changes: 17 additions & 2 deletions llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -7380,12 +7380,27 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
return false;

SDValue VScale = N.getOperand(1);
if (VScale.getOpcode() != ISD::VSCALE)
int64_t MulImm = std::numeric_limits<int64_t>::max();
if (VScale.getOpcode() == ISD::VSCALE)
MulImm = cast<ConstantSDNode>(VScale.getOperand(0))->getSExtValue();
else if (auto C = dyn_cast<ConstantSDNode>(VScale)) {
int64_t ByteOffset = C->getSExtValue();
constexpr auto SVEBitsPerBlock = AArch64::SVEBitsPerBlock;
auto MinVScale = Subtarget->getMinSVEVectorSizeInBits() / SVEBitsPerBlock;
auto MaxVScale = Subtarget->getMaxSVEVectorSizeInBits() / SVEBitsPerBlock;

if (!MaxVScale || MinVScale != MaxVScale || ByteOffset % MaxVScale != 0)
return false;

MulImm = ByteOffset / MaxVScale;
} else
return false;

assert(MulImm != std::numeric_limits<int64_t>::max() &&
"Uninitialized MulImm.");

TypeSize TS = MemVT.getSizeInBits();
int64_t MemWidthBytes = static_cast<int64_t>(TS.getKnownMinValue()) / 8;
int64_t MulImm = cast<ConstantSDNode>(VScale.getOperand(0))->getSExtValue();

if ((MulImm % MemWidthBytes) != 0)
return false;
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