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[Xtensa] Implement sextload i8 #106053

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Merged
merged 2 commits into from
Aug 26, 2024
Merged

[Xtensa] Implement sextload i8 #106053

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68abaf1
[Xtensa] Implement sextload i8.
andreisfr Aug 25, 2024
625086e
[Xtensa] Fix load test
andreisfr Aug 26, 2024
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3 changes: 2 additions & 1 deletion llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -70,11 +70,12 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand);

// No sign extend instructions for i1
// No sign extend instructions for i1 and sign extend load i8
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Comments should end with a period.

for (MVT VT : MVT::integer_valuetypes()) {
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FWIW you only need to set actions for legal VTs, that is only for VT == MVT::i32.

setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
}

setOperationAction(ISD::ConstantPool, PtrVT, Custom);
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12 changes: 12 additions & 0 deletions llvm/test/CodeGen/Xtensa/load.ll
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@@ -0,0 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=xtensa < %s | FileCheck %s

define signext i8 @test_load_i8(ptr %p){
; CHECK-LABEL: test_load_i8:
; CHECK: l8ui a8, a2, 0
; CHECK-NEXT: slli a8, a8, 24
; CHECK-NEXT: srai a2, a8, 24
; CHECK-NEXT: ret
%1 = load i8, ptr %p, align 1
ret i8 %1
}
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