Skip to content

[Mips] ISel zext nneg the same as sext for Mips64. #102852

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Aug 12, 2024
Merged

[Mips] ISel zext nneg the same as sext for Mips64. #102852

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
33c9e6f
[Mips] ISel zext nneg the same as sext for Mips64.
topperc Aug 12, 2024
ba2775a
fixup! move new PatFrags to TargetSelectionDAG.td.
topperc Aug 12, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
7 changes: 7 additions & 0 deletions llvm/include/llvm/Target/TargetSelectionDAG.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1079,6 +1079,13 @@ def zanyext : PatFrags<(ops node:$op),
[(zext node:$op),
(anyext node:$op)]>;

def zext_nneg : PatFrag<(ops node:$src), (zext node:$src), [{
return N->getFlags().hasNonNeg();
}]>;
def sext_like : PatFrags<(ops node:$src),
[(zext_nneg node:$src),
(sext node:$src)]>;

// null_frag - The null pattern operator is used in multiclass instantiations
// which accept an SDPatternOperator for use in matching patterns for internal
// definitions. When expanding a pattern, if the null fragment is referenced
Expand Down
26 changes: 13 additions & 13 deletions llvm/lib/Target/Mips/Mips64InstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -843,7 +843,7 @@ def : MipsPat<(i64 (anyext GPR32:$src)),
ISA_MIPS3, GPR_64;
def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>,
ISA_MIPS3, GPR_64;
def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>, ISA_MIPS3,
def : MipsPat<(i64 (sext_like GPR32:$src)), (SLL64_32 GPR32:$src)>, ISA_MIPS3,
GPR_64;

let AdditionalPredicates = [NotInMicroMips] in {
Expand Down Expand Up @@ -911,40 +911,40 @@ def : MipsPat<(atomic_store_64 GPR64:$v, addr:$a), (SD GPR64:$v, addr:$a)>,

// Patterns used for matching away redundant sign extensions.
// MIPS32 arithmetic instructions sign extend their result implicitly.
def : MipsPat<(i64 (sext (i32 (add GPR32:$src, immSExt16:$imm16)))),
def : MipsPat<(i64 (sext_like (i32 (add GPR32:$src, immSExt16:$imm16)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(ADDiu GPR32:$src, immSExt16:$imm16), sub_32)>;
def : MipsPat<(i64 (sext (i32 (add GPR32:$src, GPR32:$src2)))),
def : MipsPat<(i64 (sext_like (i32 (add GPR32:$src, GPR32:$src2)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(ADDu GPR32:$src, GPR32:$src2), sub_32)>;
def : MipsPat<(i64 (sext (i32 (sub GPR32:$src, GPR32:$src2)))),
def : MipsPat<(i64 (sext_like (i32 (sub GPR32:$src, GPR32:$src2)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(SUBu GPR32:$src, GPR32:$src2), sub_32)>;
def : MipsPat<(i64 (sext (i32 (mul GPR32:$src, GPR32:$src2)))),
def : MipsPat<(i64 (sext_like (i32 (mul GPR32:$src, GPR32:$src2)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(MUL GPR32:$src, GPR32:$src2), sub_32)>, ISA_MIPS32_NOT_32R6_64R6;
def : MipsPat<(i64 (sext (i32 (MipsMFHI ACC64:$src)))),
def : MipsPat<(i64 (sext_like (i32 (MipsMFHI ACC64:$src)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(PseudoMFHI ACC64:$src), sub_32)>;
def : MipsPat<(i64 (sext (i32 (MipsMFLO ACC64:$src)))),
def : MipsPat<(i64 (sext_like (i32 (MipsMFLO ACC64:$src)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(PseudoMFLO ACC64:$src), sub_32)>;
def : MipsPat<(i64 (sext (i32 (shl GPR32:$src, immZExt5:$imm5)))),
def : MipsPat<(i64 (sext_like (i32 (shl GPR32:$src, immZExt5:$imm5)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(SLL GPR32:$src, immZExt5:$imm5), sub_32)>;
def : MipsPat<(i64 (sext (i32 (shl GPR32:$src, GPR32:$src2)))),
def : MipsPat<(i64 (sext_like (i32 (shl GPR32:$src, GPR32:$src2)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(SLLV GPR32:$src, GPR32:$src2), sub_32)>;
def : MipsPat<(i64 (sext (i32 (srl GPR32:$src, immZExt5:$imm5)))),
def : MipsPat<(i64 (sext_like (i32 (srl GPR32:$src, immZExt5:$imm5)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(SRL GPR32:$src, immZExt5:$imm5), sub_32)>;
def : MipsPat<(i64 (sext (i32 (srl GPR32:$src, GPR32:$src2)))),
def : MipsPat<(i64 (sext_like (i32 (srl GPR32:$src, GPR32:$src2)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(SRLV GPR32:$src, GPR32:$src2), sub_32)>;
def : MipsPat<(i64 (sext (i32 (sra GPR32:$src, immZExt5:$imm5)))),
def : MipsPat<(i64 (sext_like (i32 (sra GPR32:$src, immZExt5:$imm5)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(SRA GPR32:$src, immZExt5:$imm5), sub_32)>;
def : MipsPat<(i64 (sext (i32 (sra GPR32:$src, GPR32:$src2)))),
def : MipsPat<(i64 (sext_like (i32 (sra GPR32:$src, GPR32:$src2)))),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
(SRAV GPR32:$src, GPR32:$src2), sub_32)>;

Expand Down
31 changes: 12 additions & 19 deletions llvm/test/CodeGen/Mips/bittest.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -53,23 +53,22 @@ define signext i32 @bittest_10_i32(i32 signext %a) nounwind {
; MIPS64: # %bb.0:
; MIPS64-NEXT: andi $1, $4, 1024
; MIPS64-NEXT: sltiu $1, $1, 1
; MIPS64-NEXT: dsll $1, $1, 32
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: dsrl $2, $1, 32
; MIPS64-NEXT: sll $2, $1, 0
;
; MIPS64R2-LABEL: bittest_10_i32:
; MIPS64R2: # %bb.0:
; MIPS64R2-NEXT: andi $1, $4, 1024
; MIPS64R2-NEXT: sltiu $1, $1, 1
; MIPS64R2-NEXT: jr $ra
; MIPS64R2-NEXT: dext $2, $1, 0, 32
; MIPS64R2-NEXT: sll $2, $1, 0
;
; MIPS64R6-LABEL: bittest_10_i32:
; MIPS64R6: # %bb.0:
; MIPS64R6-NEXT: andi $1, $4, 1024
; MIPS64R6-NEXT: sltiu $1, $1, 1
; MIPS64R6-NEXT: jr $ra
; MIPS64R6-NEXT: dext $2, $1, 0, 32
; MIPS64R6-NEXT: sll $2, $1, 0
;
; MM32R3-LABEL: bittest_10_i32:
; MM32R3: # %bb.0:
Expand Down Expand Up @@ -111,23 +110,22 @@ define signext i32 @bittest_15_i32(i32 signext %a) nounwind {
; MIPS64: # %bb.0:
; MIPS64-NEXT: andi $1, $4, 32768
; MIPS64-NEXT: sltiu $1, $1, 1
; MIPS64-NEXT: dsll $1, $1, 32
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: dsrl $2, $1, 32
; MIPS64-NEXT: sll $2, $1, 0
;
; MIPS64R2-LABEL: bittest_15_i32:
; MIPS64R2: # %bb.0:
; MIPS64R2-NEXT: andi $1, $4, 32768
; MIPS64R2-NEXT: sltiu $1, $1, 1
; MIPS64R2-NEXT: jr $ra
; MIPS64R2-NEXT: dext $2, $1, 0, 32
; MIPS64R2-NEXT: sll $2, $1, 0
;
; MIPS64R6-LABEL: bittest_15_i32:
; MIPS64R6: # %bb.0:
; MIPS64R6-NEXT: andi $1, $4, 32768
; MIPS64R6-NEXT: sltiu $1, $1, 1
; MIPS64R6-NEXT: jr $ra
; MIPS64R6-NEXT: dext $2, $1, 0, 32
; MIPS64R6-NEXT: sll $2, $1, 0
;
; MM32R3-LABEL: bittest_15_i32:
; MM32R3: # %bb.0:
Expand Down Expand Up @@ -171,23 +169,22 @@ define signext i32 @bittest_16_i32(i32 signext %a) nounwind {
; MIPS64-NEXT: not $1, $4
; MIPS64-NEXT: srl $1, $1, 16
; MIPS64-NEXT: andi $1, $1, 1
; MIPS64-NEXT: dsll $1, $1, 32
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: dsrl $2, $1, 32
; MIPS64-NEXT: sll $2, $1, 0
;
; MIPS64R2-LABEL: bittest_16_i32:
; MIPS64R2: # %bb.0:
; MIPS64R2-NEXT: not $1, $4
; MIPS64R2-NEXT: ext $1, $1, 16, 1
; MIPS64R2-NEXT: jr $ra
; MIPS64R2-NEXT: dext $2, $1, 0, 32
; MIPS64R2-NEXT: sll $2, $1, 0
;
; MIPS64R6-LABEL: bittest_16_i32:
; MIPS64R6: # %bb.0:
; MIPS64R6-NEXT: not $1, $4
; MIPS64R6-NEXT: ext $1, $1, 16, 1
; MIPS64R6-NEXT: jr $ra
; MIPS64R6-NEXT: dext $2, $1, 0, 32
; MIPS64R6-NEXT: sll $2, $1, 0
;
; MM32R3-LABEL: bittest_16_i32:
; MM32R3: # %bb.0:
Expand Down Expand Up @@ -228,24 +225,20 @@ define signext i32 @bittest_31_i32(i32 signext %a) nounwind {
; MIPS64-LABEL: bittest_31_i32:
; MIPS64: # %bb.0:
; MIPS64-NEXT: not $1, $4
; MIPS64-NEXT: srl $1, $1, 31
; MIPS64-NEXT: dsll $1, $1, 32
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: dsrl $2, $1, 32
; MIPS64-NEXT: srl $2, $1, 31
;
; MIPS64R2-LABEL: bittest_31_i32:
; MIPS64R2: # %bb.0:
; MIPS64R2-NEXT: not $1, $4
; MIPS64R2-NEXT: srl $1, $1, 31
; MIPS64R2-NEXT: jr $ra
; MIPS64R2-NEXT: dext $2, $1, 0, 32
; MIPS64R2-NEXT: srl $2, $1, 31
;
; MIPS64R6-LABEL: bittest_31_i32:
; MIPS64R6: # %bb.0:
; MIPS64R6-NEXT: not $1, $4
; MIPS64R6-NEXT: srl $1, $1, 31
; MIPS64R6-NEXT: jr $ra
; MIPS64R6-NEXT: dext $2, $1, 0, 32
; MIPS64R6-NEXT: srl $2, $1, 31
;
; MM32R3-LABEL: bittest_31_i32:
; MM32R3: # %bb.0:
Expand Down
Loading