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bugzillaIssues migrated from bugzillaIssues migrated from bugzillacrashPrefer [crash-on-valid] or [crash-on-invalid]Prefer [crash-on-valid] or [crash-on-invalid]llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well
Description
Bugzilla Link | 20147 |
Version | trunk |
OS | Linux |
Reporter | LLVM Bugzilla Contributor |
CC | @jmolloy,@TNorthover |
Extended Description
In r211960, I fixed an ICE in getMemsetValue.
The segment of code just below the fix looks suspect as well, but I was unable to generate a test case in my quick attempt.
Specifically, line 3638 seems to assume the VT of a vector element is either f32 or f64.
3636 else if (VT.isVector()) {
3637 unsigned NumElts = VT.getVectorNumElements();
3638 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
3639 return DAG.getNode(ISD::BITCAST, dl, VT,
3640 DAG.getConstant(0, EVT::getVectorVT(*DAG.getContext(),
3641 EltVT, NumElts)));
3642 } else
Hoping someone wouldn't mind taking a look.
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bugzillaIssues migrated from bugzillaIssues migrated from bugzillacrashPrefer [crash-on-valid] or [crash-on-invalid]Prefer [crash-on-valid] or [crash-on-invalid]llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well