Move to OpTy::create, OpBuilder::create is deprecated.

docs/Dialects/Comb/RationaleComb.md

@@ -272,9 +272,9 @@ zero of a list is the leftmost operand in assembly, which is the most
 significant value.
 
 ```cpp
-ConcatOp result = builder.create<ConcatOp>(..., {msb, lsb});
+ConcatOp result = ConcatOp::create(builder, ..., {msb, lsb});
 // Is equivalent to the above integer concatenation example.
-ArrayConcatOp arr = builder.create<ArrayConcatOp>(..., {arr123, arr456});
+ArrayConcatOp arr = ArrayConcatOp::create(builder, ..., {arr123, arr456});
 // Is equivalent to the above array example.
 ```
 

include/circt/Dialect/Calyx/CalyxHelpers.h

@@ -70,8 +70,8 @@ static void updateGroupAssignmentGuards(OpBuilder &builder, GroupOp &group,
     if (assign.getGuard())
       // If the assignment is guarded already, take the bitwise & of the current
       // guard and the group's go signal.
-      assign->setOperand(2, builder.create<comb::AndOp>(
-                                group.getLoc(), assign.getGuard(), op, false));
+      assign->setOperand(2, comb::AndOp::create(builder, group.getLoc(),
+                                                assign.getGuard(), op, false));
     else
       // Otherwise, just insert it as the guard.
       assign->insertOperands(2, {op});

include/circt/Dialect/Calyx/CalyxLoweringUtils.h

@@ -74,7 +74,7 @@ TGroup createGroup(OpBuilder &builder, calyx::ComponentOp compOp, Location loc,
                    Twine uniqueName) {
   mlir::IRRewriter::InsertionGuard guard(builder);
   builder.setInsertionPointToEnd(compOp.getWiresOp().getBodyBlock());
-  return builder.create<TGroup>(loc, uniqueName.str());
+  return TGroup::create(builder, loc, uniqueName.str());
 }
 
 /// Creates register assignment operations within the provided groupOp.
@@ -468,7 +468,7 @@ class ComponentLoweringStateInterface {
       }
       }
     }
-    return builder.create<TLibraryOp>(loc, getUniqueName(name), resTypes);
+    return TLibraryOp::create(builder, loc, getUniqueName(name), resTypes);
   }
 
   llvm::json::Value &getExtMemData() { return extMemData; }

include/circt/Dialect/FIRRTL/FIRRTLCanonicalization.td

@@ -318,7 +318,7 @@ def SubFromZeroUnsigned : Pat <
 //sub(a,a) -> 0
 def SubOfSelf : Pat <
   (SubPrimOp:$old $x, $x),
-  (NativeCodeCall<"$_builder.create<ConstantOp>($0.getLoc(), type_cast<IntType>($0.getType()), getIntZerosAttr($0.getType()))"> $old),
+  (NativeCodeCall<"ConstantOp::create($_builder, $0.getLoc(), type_cast<IntType>($0.getType()), getIntZerosAttr($0.getType()))"> $old),
   [(KnownWidth $x)]>;
 
 // sub((pad a, n), b) -> pad(sub(a, b), n)
@@ -336,7 +336,7 @@ def SubOfPadR : Pat <
 // and(x, 0) -> 0, fold can't handle all cases
 def AndOfZero : Pat <
   (AndPrimOp:$old $x, (ConstantOp:$zcst $cst)),
-  (NativeCodeCall<"$_builder.create<ConstantOp>($0.getLoc(), type_cast<IntType>($0.getType()), getIntZerosAttr($0.getType()))"> $old),
+  (NativeCodeCall<"ConstantOp::create($_builder, $0.getLoc(), type_cast<IntType>($0.getType()), getIntZerosAttr($0.getType()))"> $old),
   [(KnownWidth $x), (ZeroConstantOp $zcst)]>;
 
 // and(x, -1) -> x, fold can't handle all cases
@@ -378,7 +378,7 @@ def OrOfZero : Pat <
 // or(x, -1) -> -1, fold can't handle all cases
 def OrOfAllOne : Pat <
   (OrPrimOp:$old $x, (ConstantOp:$ocst $cst)),
-  (NativeCodeCall<"$_builder.create<ConstantOp>($0.getLoc(), type_cast<IntType>($0.getType()), getIntOnesAttr($0.getType()))"> $old),
+  (NativeCodeCall<"ConstantOp::create($_builder, $0.getLoc(), type_cast<IntType>($0.getType()), getIntOnesAttr($0.getType()))"> $old),
   [(KnownWidth $x), (EqualTypes $x, $ocst), (AllOneConstantOp $ocst)]>;
 
 /// or(x,x) -> x, fold can't handle all cases
@@ -410,7 +410,7 @@ def XorOfZero : Pat <
 /// xor(x,x) -> 0, fold can't handle all cases
 def XorOfSelf : Pat <
   (XorPrimOp:$old $x, $x),
-  (NativeCodeCall<"$_builder.create<ConstantOp>($0.getLoc(), type_cast<IntType>($0.getType()), getIntZerosAttr($0.getType()))"> $old),
+  (NativeCodeCall<"ConstantOp::create($_builder, $0.getLoc(), type_cast<IntType>($0.getType()), getIntZerosAttr($0.getType()))"> $old),
   [(KnownWidth $x)]>;
 
 /// xor(x, pad(y, n)) -> cat(head(x), xor(tail(x), y))
@@ -496,7 +496,7 @@ def AndRasUInt : Pat <
 /// andr(pad(x:U,n)) -> 0 (where pad is doing something)
 def AndRPadU : Pat <
   (AndRPrimOp:$old (PadPrimOp:$pad $x, $n)),
-  (NativeCodeCall<"$_builder.create<ConstantOp>($0.getLoc(), type_cast<IntType>($0.getType()), getIntZerosAttr($0.getType()))"> $old),
+  (NativeCodeCall<"ConstantOp::create($_builder, $0.getLoc(), type_cast<IntType>($0.getType()), getIntZerosAttr($0.getType()))"> $old),
   [(KnownWidth $x), (UIntTypes $x), (IntTypeWidthGT32 $pad, $x)]>;
 
 /// andr(pad(x:S,n)) -> andr(x)

include/circt/Dialect/SSP/Utilities.h

@@ -437,35 +437,35 @@ saveProblem(ProblemT &prob, std::tuple<OperationPropertyTs...> opProps,
   ImplicitLocOpBuilder b(builder.getUnknownLoc(), builder);
 
   // Set up instance.
-  auto instOp = b.create<InstanceOp>(
-      builder.getStringAttr(ProblemT::name),
+  auto instOp = InstanceOp::create(
+      b, builder.getStringAttr(ProblemT::name),
       saveInstanceProperties<ProblemT, InstancePropertyTs...>(prob, b));
   if (auto instName = prob.getInstanceName())
     instOp.setSymNameAttr(instName);
 
   // Emit operator types.
   b.setInsertionPointToEnd(instOp.getBodyBlock());
-  auto libraryOp = b.create<OperatorLibraryOp>();
+  auto libraryOp = OperatorLibraryOp::create(b);
   if (auto libName = prob.getLibraryName())
     libraryOp.setSymNameAttr(libName);
   b.setInsertionPointToStart(libraryOp.getBodyBlock());
 
   for (auto opr : prob.getOperatorTypes())
-    b.create<OperatorTypeOp>(
-        opr.getAttr(),
+    OperatorTypeOp::create(
+        b, opr.getAttr(),
         saveOperatorTypeProperties<ProblemT, OperatorTypePropertyTs...>(
             prob, opr, b));
 
   // Emit resource types.
   b.setInsertionPointToEnd(instOp.getBodyBlock());
-  auto rsrcLibraryOp = b.create<ResourceLibraryOp>();
+  auto rsrcLibraryOp = ResourceLibraryOp::create(b);
   if (auto rsrcLibName = prob.getRsrcLibraryName())
     rsrcLibraryOp.setSymNameAttr(rsrcLibName);
   b.setInsertionPointToStart(rsrcLibraryOp.getBodyBlock());
 
   for (auto rsrc : prob.getResourceTypes())
-    b.create<ResourceTypeOp>(
-        rsrc.getAttr(),
+    ResourceTypeOp::create(
+        b, rsrc.getAttr(),
         saveResourceTypeProperties<ProblemT, ResourceTypePropertyTs...>(
             prob, rsrc, b));
 
@@ -490,7 +490,7 @@ saveProblem(ProblemT &prob, std::tuple<OperationPropertyTs...> opProps,
 
   // Construct operations and model their dependences.
   b.setInsertionPointToEnd(instOp.getBodyBlock());
-  auto graphOp = b.create<DependenceGraphOp>();
+  auto graphOp = DependenceGraphOp::create(b);
   b.setInsertionPointToStart(graphOp.getBodyBlock());
 
   BackedgeBuilder backedgeBuilder(b, b.getLoc());
@@ -534,8 +534,8 @@ saveProblem(ProblemT &prob, std::tuple<OperationPropertyTs...> opProps,
     // NB: sym_name, dependences and properties are optional attributes, so
     // passing potentially unitialized String/ArrayAttrs is intentional here.
     auto opOp =
-        b.create<OperationOp>(op->getNumResults(), v.get(op->getOperands()),
-                              opNames.lookup(op), dependences, properties);
+        OperationOp::create(b, op->getNumResults(), v.get(op->getOperands()),
+                            opNames.lookup(op), dependences, properties);
     v.set(op->getResults(), opOp->getResults());
   }
 

include/circt/Support/BackedgeBuilder.h

@@ -39,7 +39,7 @@ class Backedge;
 ///   circt::BackedgeBuilder back(rewriter, loc);
 ///   circt::Backedge ready = back.get(rewriter.getI1Type());
 ///   // Use `ready` as a `Value`.
-///   auto addOp = rewriter.create<addOp>(loc, ready);
+///   auto addOp = addOp::create(rewriter, loc, ready);
 ///   // When the actual value is available,
 ///   ready.set(anotherOp.getResult(0));
 /// ```

lib/Conversion/CFToHandshake/CFToHandshake.cpp

@@ -947,20 +947,21 @@ BufferOp LoopNetworkRewriter::buildContinueNetwork(Block *loopHeader,
 
   // Merge all of the controls in each partition
   rewriter->setInsertionPointToStart(loopHeader);
-  auto externalCtrlMerge = rewriter->create<ControlMergeOp>(loc, externalCtrls);
+  auto externalCtrlMerge =
+      ControlMergeOp::create(*rewriter, loc, externalCtrls);
 
   // Create loop mux and the loop priming register. The loop mux will on select
   // "0" select external control, and internal control at "1". This convention
   // must be followed by the loop exit network.
-  auto primingRegister =
-      rewriter->create<BufferOp>(loc, loopPrimingInput, 1, BufferTypeEnum::seq);
+  auto primingRegister = BufferOp::create(*rewriter, loc, loopPrimingInput, 1,
+                                          BufferTypeEnum::seq);
   // Initialize the priming register to path 0.
   primingRegister->setAttr("initValues", rewriter->getI64ArrayAttr({0}));
 
   // The loop control mux will deterministically select between control entering
   // the loop from any external block or the single loop backedge.
-  auto loopCtrlMux = rewriter->create<MuxOp>(
-      loc, primingRegister.getResult(),
+  auto loopCtrlMux = MuxOp::create(
+      *rewriter, loc, primingRegister.getResult(),
       llvm::SmallVector<Value>{externalCtrlMerge.getResult(), loopCtrl});
 
   // Replace the existing control merge 'result' output with the loop control
@@ -999,14 +1000,13 @@ BufferOp LoopNetworkRewriter::buildContinueNetwork(Block *loopHeader,
   // loop latch, will then be selected between by a 3rd mux, based on the
   // priming register.
   for (MuxOp mux : muxesToReplace) {
-    auto externalDataMux = rewriter->create<MuxOp>(
-        loc, externalCtrlMerge.getIndex(), externalDataInputs[mux]);
+    auto externalDataMux = MuxOp::create(
+        *rewriter, loc, externalCtrlMerge.getIndex(), externalDataInputs[mux]);
 
     rewriter->replaceOp(
-        mux, rewriter
-                 ->create<MuxOp>(loc, primingRegister,
-                                 llvm::SmallVector<Value>{externalDataMux,
-                                                          loopDataInputs[mux]})
+        mux, MuxOp::create(
+                 *rewriter, loc, primingRegister,
+                 llvm::SmallVector<Value>{externalDataMux, loopDataInputs[mux]})
                  .getResult());
   }
 
@@ -1049,17 +1049,18 @@ void LoopNetworkRewriter::buildExitNetwork(
       // This goes against the convention, and we have to invert the condition
       // value before connecting it to the exit network.
       rewriter->setInsertionPoint(condBr);
-      condValue = rewriter->create<arith::XOrIOp>(
-          loc, condValue.getType(), condValue,
-          rewriter->create<arith::ConstantOp>(
-              loc, rewriter->getIntegerAttr(rewriter->getI1Type(), 1)));
+      condValue = arith::XOrIOp::create(
+          *rewriter, loc, condValue.getType(), condValue,
+          arith::ConstantOp::create(
+              *rewriter, loc,
+              rewriter->getIntegerAttr(rewriter->getI1Type(), 1)));
     }
     parityCorrectedConds.push_back(condValue);
   }
 
   // Merge all of the parity-corrected exit conditions and assign them
   // to the loop priming input.
-  auto exitMerge = rewriter->create<MergeOp>(loc, parityCorrectedConds);
+  auto exitMerge = MergeOp::create(*rewriter, loc, parityCorrectedConds);
   loopPrimingInput.setValue(exitMerge);
 }
 

lib/Conversion/CalyxToFSM/RemoveGroupsFromFSM.cpp

@@ -104,8 +104,8 @@ LogicalResult CalyxRemoveGroupsFromFSM::modifyGroupOperations() {
     auto doneWire = doneWireIt->second;
 
     b->setInsertionPointToEnd(componentOp.getWiresOp().getBodyBlock());
-    b->create<calyx::AssignOp>(loc, doneWire.getIn(), groupDone.getSrc(),
-                               groupDone.getGuard());
+    calyx::AssignOp::create(*b, loc, doneWire.getIn(), groupDone.getSrc(),
+                            groupDone.getGuard());
 
     groupDone.erase();
   }
@@ -217,8 +217,8 @@ LogicalResult CalyxRemoveGroupsFromFSM::outlineMachine() {
 
     // Create a wire for the group done input.
     b->setInsertionPointToStart(&componentOp.getBody().front());
-    auto groupDoneWire = b->create<calyx::WireLibOp>(
-        componentOp.getLoc(), name.str() + "_done", b->getI1Type());
+    auto groupDoneWire = calyx::WireLibOp::create(
+        *b, componentOp.getLoc(), name.str() + "_done", b->getI1Type());
     fsmInputMap[inputIdx] = groupDoneWire.getOut();
     groupDoneWires[name] = groupDoneWire;
   }
@@ -264,10 +264,11 @@ LogicalResult CalyxRemoveGroupsFromFSM::outlineMachine() {
 
   // Instantiate the FSM.
   auto clkPort = componentOp.getClkPort();
-  auto clk = b->create<seq::ToClockOp>(clkPort.getLoc(), clkPort);
-  auto fsmInstance = b->create<fsm::HWInstanceOp>(
-      machineOp.getLoc(), machineOutputTypes, b->getStringAttr("controller"),
-      machineOp.getSymNameAttr(), fsmInputs, clk, componentOp.getResetPort());
+  auto clk = seq::ToClockOp::create(*b, clkPort.getLoc(), clkPort);
+  auto fsmInstance = fsm::HWInstanceOp::create(
+      *b, machineOp.getLoc(), machineOutputTypes,
+      b->getStringAttr("controller"), machineOp.getSymNameAttr(), fsmInputs,
+      clk, componentOp.getResetPort());
 
   // Record the FSM output group go signals.
   for (auto namedAttr : groupGoOutputsAttr.getValue()) {
@@ -278,8 +279,8 @@ LogicalResult CalyxRemoveGroupsFromFSM::outlineMachine() {
 
   // Assign FSM top level done to the component done.
   b->setInsertionPointToEnd(componentOp.getWiresOp().getBodyBlock());
-  b->create<calyx::AssignOp>(machineOp.getLoc(), componentOp.getDonePort(),
-                             fsmInstance.getResult(topLevelDoneAttr.getInt()));
+  calyx::AssignOp::create(*b, machineOp.getLoc(), componentOp.getDonePort(),
+                          fsmInstance.getResult(topLevelDoneAttr.getInt()));
 
   return success();
 }

lib/Conversion/DatapathToComb/DatapathToComb.cpp

@@ -472,8 +472,9 @@ struct DatapathPosPartialProductOpConversion
 
     // Compute 2*c for use in array construction
     Value zero = hw::ConstantOp::create(rewriter, loc, APInt(1, 0));
-    Value twoCWider = rewriter.create<comb::ConcatOp>(loc, ValueRange{c, zero});
-    Value twoC = rewriter.create<comb::ExtractOp>(loc, twoCWider, 0, rowWidth);
+    Value twoCWider =
+        comb::ConcatOp::create(rewriter, loc, ValueRange{c, zero});
+    Value twoC = comb::ExtractOp::create(rewriter, loc, twoCWider, 0, rowWidth);
 
     // AND Array Construction:
     // pp[i] = ( (carry[i] * (c<<1)) | (save[i] * c) ) << i

lib/Conversion/HWToLLVM/HWToLLVM.cpp

@@ -157,39 +157,43 @@ struct ArrayInjectOpConversion
       return success();
     }
 
-    auto oneC = rewriter.create<LLVM::ConstantOp>(
-        op->getLoc(), rewriter.getI32Type(), rewriter.getI32IntegerAttr(1));
+    auto oneC =
+        LLVM::ConstantOp::create(rewriter, op->getLoc(), rewriter.getI32Type(),
+                                 rewriter.getI32IntegerAttr(1));
     auto zextIndex = zextByOne(op->getLoc(), rewriter, op.getIndex());
 
     Value arrPtr;
     if (arrElems == 1 || !llvm::isPowerOf2_64(arrElems)) {
       // Clamp index to prevent OOB access. We add an extra element to the
       // array so that OOB access modifies this element, leaving the original
       // array intact.
-      auto maxIndex = rewriter.create<LLVM::ConstantOp>(
-          op->getLoc(), zextIndex.getType(),
-          rewriter.getI32IntegerAttr(arrElems));
+      auto maxIndex =
+          LLVM::ConstantOp::create(rewriter, op->getLoc(), zextIndex.getType(),
+                                   rewriter.getI32IntegerAttr(arrElems));
       zextIndex =
-          rewriter.create<LLVM::UMinOp>(op->getLoc(), zextIndex, maxIndex);
+          LLVM::UMinOp::create(rewriter, op->getLoc(), zextIndex, maxIndex);
 
       newArrTy = typeConverter->convertType(
           hw::ArrayType::get(inputType.getElementType(), arrElems + 1));
-      arrPtr = rewriter.create<LLVM::AllocaOp>(
-          op->getLoc(), LLVM::LLVMPointerType::get(rewriter.getContext()),
-          newArrTy, oneC, /*alignment=*/4);
+      arrPtr = LLVM::AllocaOp::create(
+          rewriter, op->getLoc(),
+          LLVM::LLVMPointerType::get(rewriter.getContext()), newArrTy, oneC,
+          /*alignment=*/4);
     } else {
-      arrPtr = rewriter.create<LLVM::AllocaOp>(
-          op->getLoc(), LLVM::LLVMPointerType::get(rewriter.getContext()),
-          newArrTy, oneC, /*alignment=*/4);
+      arrPtr = LLVM::AllocaOp::create(
+          rewriter, op->getLoc(),
+          LLVM::LLVMPointerType::get(rewriter.getContext()), newArrTy, oneC,
+          /*alignment=*/4);
     }
 
-    rewriter.create<LLVM::StoreOp>(op->getLoc(), adaptor.getInput(), arrPtr);
+    LLVM::StoreOp::create(rewriter, op->getLoc(), adaptor.getInput(), arrPtr);
 
-    auto gep = rewriter.create<LLVM::GEPOp>(
-        op->getLoc(), LLVM::LLVMPointerType::get(rewriter.getContext()),
-        newArrTy, arrPtr, ArrayRef<LLVM::GEPArg>{0, zextIndex});
+    auto gep = LLVM::GEPOp::create(
+        rewriter, op->getLoc(),
+        LLVM::LLVMPointerType::get(rewriter.getContext()), newArrTy, arrPtr,
+        ArrayRef<LLVM::GEPArg>{0, zextIndex});
 
-    rewriter.create<LLVM::StoreOp>(op->getLoc(), adaptor.getElement(), gep);
+    LLVM::StoreOp::create(rewriter, op->getLoc(), adaptor.getElement(), gep);
     rewriter.replaceOpWithNewOp<LLVM::LoadOp>(op, oldArrTy, arrPtr);
     return success();
   }

lib/Conversion/HandshakeToHW/HandshakeToHW.cpp

@@ -1826,9 +1826,9 @@ class ExtModuleConversionPattern : public OpConversionPattern<T> {
     hw::HWModuleLike implModule = checkSubModuleOp(ls.parentModule, op);
     if (!implModule) {
       auto portInfo = ModulePortInfo(getPortInfoForOp(op));
-      implModule = submoduleBuilder.create<hw::HWModuleExternOp>(
-          op.getLoc(), submoduleBuilder.getStringAttr(getSubModuleName(op)),
-          portInfo);
+      implModule = hw::HWModuleExternOp::create(
+          submoduleBuilder, op.getLoc(),
+          submoduleBuilder.getStringAttr(getSubModuleName(op)), portInfo);
     }
 
     llvm::SmallVector<Value> operands = adaptor.getOperands();

lib/Conversion/ImportVerilog/Structure.cpp

@@ -1096,8 +1096,8 @@ static LogicalResult rewriteCallSitesToPassCaptures(mlir::func::FuncOp callee,
 
     OpBuilder b(call);
     auto flatRef = mlir::FlatSymbolRefAttr::get(callee);
-    auto newCall = b.create<mlir::func::CallOp>(call.getLoc(), fTy.getResults(),
-                                                flatRef, newOperands);
+    auto newCall = mlir::func::CallOp::create(
+        b, call.getLoc(), fTy.getResults(), flatRef, newOperands);
     call->replaceAllUsesWith(newCall.getOperation());
     call->erase();
   }

lib/Conversion/MooreToCore/MooreToCore.cpp

@@ -1738,9 +1738,9 @@ static LogicalResult convert(SeverityBIOp op, SeverityBIOp::Adaptor adaptor,
   }
 
   auto prefix =
-      rewriter.create<sim::FormatLiteralOp>(op.getLoc(), severityString);
-  auto message = rewriter.create<sim::FormatStringConcatOp>(
-      op.getLoc(), ValueRange{prefix, adaptor.getMessage()});
+      sim::FormatLiteralOp::create(rewriter, op.getLoc(), severityString);
+  auto message = sim::FormatStringConcatOp::create(
+      rewriter, op.getLoc(), ValueRange{prefix, adaptor.getMessage()});
   rewriter.replaceOpWithNewOp<sim::PrintFormattedProcOp>(op, message);
   return success();
 }

lib/Conversion/SeqToSV/FirRegLowering.h

@@ -164,7 +164,7 @@ class FirRegLowering {
       return constant;
     }
 
-    constant = builder.create<hw::ConstantOp>(loc, value);
+    constant = hw::ConstantOp::create(builder, loc, value);
     return constant;
   }