[ImportVerilog] Support real-to-integer conversion in format string #9123
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Extend `FormatStringParser::emitInteger` to correctly handle **real-typed (`shortreal`/`real`) arguments** when emitting `%d`, `%h`, etc. format specifiers during import.
- Detect if the expression’s type is `moore::RealType`.
- For real operands:
- Compute required integer width based on IEEE-754 format:
- `shortreal` (binary32) → **129-bit signed integer**
- `real` (binary64) → **1025-bit signed integer**
- Insert a `moore::RealToIntOp` cast before integer formatting.
- Non-real (integral) values continue to use existing conversion logic.
- Ensures real values print correctly via implicit real-to-integer conversion.
fabianschuiki
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Oct 21, 2025
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fabianschuiki
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Holy cow, you can print reals with %d in Verilog 🤯? LGTM!
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You should've seen my face when I first figured that out, and then again when I figured out how wide that integer would have to be 🙈 |
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Extend
FormatStringParser::emitIntegerto correctly handle real-typed (shortreal/real) arguments when emitting%d,%h, etc. format specifiers during import.moore::RealType.shortreal(binary32) → 129-bit signed integerreal(binary64) → 1025-bit signed integermoore::RealToIntOpcast before integer formatting.