[Moore][ImportVerilog] Add real-valued ops + real-aware import; refactor logical handling #9122

Scheremo · 2025-10-21T09:12:24Z

Introduce full real (f32/f64) operator support in the Moore dialect and the ImportVerilog conversion, including unary, arithmetic, equality, relational, logical, and ++/-- forms. Refactor logical operator lowering to a reusable helper and add comprehensive tests.

Dialect (MooreOps.td):
- New unary real op: NegRealOp -> moore.fneg.
- Real binary op base: BinaryRealOpBase for typed f32/f64 operands/results.
- Arithmetic: AddRealOp (fadd), SubRealOp (fsub), MulRealOp (fmul), DivRealOp (fdiv), PowRealOp (fpow).
- Equality: EqRealOp (feq), NeRealOp (fne).
- Relational: FltOp (flt), FleOp (fle), FgtOp (fgt), FgeOp (fge).
- All ops follow IEEE 1800-2023 §11.3.1, §11.4.3–§11.4.5 semantics.
Import (Expressions.cpp):
- Add visitRealUOp and visitRealBOp to lower real-typed unary/binary expressions.
- Implement pre/post increment/decrement for real variables via fadd/fsub with an exact APFloat "1.0" (IEEEsingle/IEEEdouble) constructor.
- Add moore.fneg for unary minus; unary plus becomes a no-op.
- Map real comparisons to feq/fne/flt/fle/fgt/fge.
- Refactor logical ops into buildLogicalBOp(...) (optional Domain param), shared by int/real paths. (Short-circuit remains TODO.)
- Route mixed/real expressions early to the real path; keep existing integral flow otherwise.
Tests (basic.sv):
- New end-to-end checks for f64/f32 arithmetic, comparisons, logicals, unary ops, and ++/--.
- Assert exact opcode emission (moore.fadd/fsub/fmul/fdiv/fpow/feq/fne/flt/fle/fgt/fge/fneg) and constant forms for 1.0.

include/circt/Dialect/Moore/MooreOps.td

lib/Conversion/ImportVerilog/Expressions.cpp

fabianschuiki · 2025-10-21T19:25:54Z

lib/Conversion/ImportVerilog/Expressions.cpp

+    Type lhsTy = context.convertType(*expr.left().type, loc);
+    Type rhsTy = context.convertType(*expr.right().type, loc);
+
+    if (!lhsTy || !rhsTy)
+      return {};
+
+    assert(lhsTy == rhsTy &&
+           "Slang should have converted both operands to the same type!");
+    Type targetTy = lhsTy;


I would use the type of the binary expression directly: expr.type. Slang computes that using the rules for operands outlined in the SV spec, including finding the widest operand width, signness matching, etc. I think it does the same thing for reals, where a shortreal + real would be determined to have type real for the + result.

That also means you don't need to assert equality on the LHS and RHS type. The assert will abort the compiler. If you don't assert, the conversions further down fail with a proper diagnostic pointing at the failing input, which is going to be much easier to debug and track down if it happens.

Yep, makes sense. Wasn't aware of expr.type but that simplifies this a lot!

A bit too much as it turns out! expr.type holds the return type, which sometimes but not always is equal to the RHS types.

fabianschuiki · 2025-10-21T19:26:35Z

lib/Conversion/ImportVerilog/Expressions.cpp

+    // First check whether we need real or integral BOps
+    const auto *rhsFloatType =
+        expr.right().type->as_if<slang::ast::FloatingType>();
+    const auto *lhsFloatType =
+        expr.left().type->as_if<slang::ast::FloatingType>();
+
+    // If either op is real-typed, treat as real BOp. Bail here.
+    if (rhsFloatType || lhsFloatType)
+      return visitRealBOp(expr);
+


Same here: I think you can just check expr.type and see if it is a float. If it is, call out to visitRealBOp.

Yep! Fixed it.

At least in here, we can't make the shortcut: a BinaryOperator::Equality will have return type i1, so this currently fails. This might also be a bug for the "normal" sbv pipeline if operands are cast to i1!

fabianschuiki

Really really cool! Thanks a lot for adding all of this 🥳 💯!

Scheremo · 2025-10-21T19:40:16Z

Really really cool! Thanks a lot for adding all of this 🥳 💯!

Thanks for the thorough review! Let's hope this fixes some more sv-tests 😄

…tor logical handling Introduce full **real (f32/f64)** operator support in the Moore dialect and the ImportVerilog conversion, including unary, arithmetic, equality, relational, logical, and ++/-- forms. Refactor logical operator lowering to a reusable helper and add comprehensive tests. - **Dialect (`MooreOps.td`):** - New unary real op: `NegRealOp` -> `moore.fneg`. - Real binary op base: `BinaryRealOpBase` for typed f32/f64 operands/results. - Arithmetic: `AddRealOp` (`fadd`), `SubRealOp` (`fsub`), `MulRealOp` (`fmul`), `DivRealOp` (`fdiv`), `PowRealOp` (`fpow`). - Equality: `EqRealOp` (`feq`), `NeRealOp` (`fne`). - Relational: `FltOp` (`flt`), `FleOp` (`fle`), `FgtOp` (`fgt`), `FgeOp` (`fge`). - All ops follow IEEE 1800-2023 §11.3.1, §11.4.3–§11.4.5 semantics. - **Import (`Expressions.cpp`):** - Add `visitRealUOp` and `visitRealBOp` to lower real-typed unary/binary expressions. - Implement pre/post **increment/decrement** for real variables via `fadd`/`fsub` with an exact `APFloat` **"1.0"** (IEEEsingle/IEEEdouble) constructor. - Add `moore.fneg` for unary minus; unary plus becomes a no-op. - Map real comparisons to `feq/fne/flt/fle/fgt/fge`. - **Refactor logical ops** into `buildLogicalBOp(...)` (optional `Domain` param), shared by int/real paths. (Short-circuit remains TODO.) - Route mixed/real expressions early to the real path; keep existing integral flow otherwise. - **Tests (`basic.sv`):** - New end-to-end checks for f64/f32 arithmetic, comparisons, logicals, unary ops, and ++/--. - Assert exact opcode emission (`moore.fadd/fsub/fmul/fdiv/fpow/feq/fne/flt/fle/fgt/fge/fneg`) and constant forms for `1.0`.

Scheremo force-pushed the pr-real-binops branch 2 times, most recently from 097315a to d56317d Compare October 21, 2025 10:59

Scheremo changed the title ~~[Moore][ImportVerilog] Add real-valued binary operations~~ [Moore][ImportVerilog] Add real-valued ops + real-aware import; refactor logical handling Oct 21, 2025

Scheremo marked this pull request as ready for review October 21, 2025 11:00

fabianschuiki reviewed Oct 21, 2025

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Scheremo force-pushed the pr-real-binops branch 3 times, most recently from 1f1bf2c to 50c009e Compare October 21, 2025 18:57

fabianschuiki added Moore ImportVerilog labels Oct 21, 2025

Scheremo force-pushed the pr-real-binops branch 3 times, most recently from fb132a4 to 658622c Compare October 21, 2025 19:21

fabianschuiki reviewed Oct 21, 2025

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Scheremo force-pushed the pr-real-binops branch 2 times, most recently from fc55461 to 15433de Compare October 21, 2025 19:33

fabianschuiki approved these changes Oct 21, 2025

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Scheremo force-pushed the pr-real-binops branch from 15433de to 93e6af8 Compare October 21, 2025 19:36

Scheremo force-pushed the pr-real-binops branch 2 times, most recently from 4d11bb2 to 39abea5 Compare October 21, 2025 20:03

Scheremo force-pushed the pr-real-binops branch from 39abea5 to 0881ad1 Compare October 21, 2025 20:06

Scheremo merged commit 9c89d1c into llvm:main Oct 21, 2025
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[Moore][ImportVerilog] Add real-valued ops + real-aware import; refactor logical handling #9122

[Moore][ImportVerilog] Add real-valued ops + real-aware import; refactor logical handling #9122

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