[ExportVerilog] Require $unsigned for outer-most expression in assignment #9024
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uenoku
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darthscsi,
dtzSiFive,
fabianschuiki and
youngar
fabianschuiki
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Sep 25, 2025
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fabianschuiki
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LGTM! Really nice that this boils down to only adjusting the signRequirement. Very neat!
seldridge
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Sep 26, 2025
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seldridge
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LGTM
This fixes observed tool warnings.
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This commit aims to fix a lint warning "assignment from signed to unsigned expression".
Fix #4891