[SV] Support expressions as case patterns

[chiahsuantw]

In the current version of CIRCT, constant expressions in case statements (see IEEE 1800-2017 §12.5.2) are not supported. This patch introduces a new case pattern kind, CaseExprPattern, which allows using expressions (SSA values) as case patterns. A simple test is included to validate this feature.

MLIR Assembly:

%foo = sv.wire : !hw.inout<i1>
%bar = sv.wire : !hw.inout<i1>
%2 = sv.read_inout %foo : !hw.inout<i1>
%3 = sv.read_inout %bar : !hw.inout<i1>
sv.initial {
  sv.case %0 : i1
  case %2: {
    sv.fwrite %fd, "foo"
  }
  case %3: {
    sv.fwrite %fd, "bar"
  }
  default: {
    sv.fwrite %fd, "default"
  }
}

Exported Verilog:

wire foo;
wire bar;
initial begin
  case (1'h1)
    foo:
      $fwrite(32'h80000002, "foo");
    bar:
      $fwrite(32'h80000002, "bar");
    default:
      $fwrite(32'h80000002, "default");
  endcase
end // initial

Implementation Details

Case patterns are determined by the types of attributes attached to sv::CaseOp:

• CaseDefaultPattern : mlir::UnitAttr
• CaseBitPattern : mlir::IntegerAttr
• CaseEnumPattern : hw::EnumFieldAttr
• CaseExprPattern : sv::CaseExprPatternAttr (proposed)

This patch introduces CaseExprPatternAttr along with a variadic list of operands, caseValues, for sv::CaseOp. Each CaseExprPatternAttr corresponds, in order, to a value in caseValues. In the example below, %5 and %6 correspond to the first and second #sv.expr, respectively. Note: %1 is the condition of the case statement.

"sv.case"(%1, %5, %6) <{casePatterns = [#sv.expr, #sv.expr, unit], caseStyle = 0 : i32, validationQualifier = #sv<validation_qualifier plain>}> ({
  "sv.fwrite"(%0) <{format_string = "foo"}> : (i32) -> ()
}, {
  "sv.fwrite"(%0) <{format_string = "bar"}> : (i32) -> ()
}, {
  "sv.fwrite"(%0) <{format_string = "default"}> : (i32) -> ()
}) : (i1, i1, i1) -> ()

[chiahsuantw]

Hi @uenoku and @fabianschuiki! I’m adding support for expressions as case patterns (as I mentioned on Discord a few weeks ago). Could you give me some feedback or suggest someone who could review it? Thanks!

[fabianschuiki]

I think this makes sense, since we already have support for bit patterns and enums in the case items anyway. Extending that to arbitrary SSA values that are checked for equality makes sense to me.

[chiahsuantw]

@fabianschuiki Appreciate the feedback! If there are no further concerns, could we proceed with merging this commit?