[ImportVerilog][Bug] Fix single argument expressions in severity tasks #8998
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This commit fixes missing support for expression evaluation in severity system tasks as well as is the `$display` and `$write` tasks. According to IEEE 1800-2023 Section 21.2.1 "The display and write tasks", it is legal to pass fully formatted expressions as the arguments of severity, display, and write tasks. In the previous implementation, it was assumed that the first argument would always be a StringLiteral in need of formatting; this commit adds a case distinction in the handling of these statements that ensures we first check whether we need to treat the arguments as a format string instance, or we are being handed a fully formatted string.
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fabianschuiki
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Sep 20, 2025
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Very nice! Thanks for finding and fixing this!
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This commit fixes missing support for expression evaluation in severity system tasks as well as is the
$displayand$writetasks.According to IEEE 1800-2023 Section 21.2.1 "The display and write tasks", it is legal to pass fully formatted expressions as the arguments of severity, display, and write tasks. In the previous implementation, it was assumed that the first argument would always be a StringLiteral in need of formatting; this commit adds a case distinction in the handling of these statements that ensures we first check whether we need to treat the arguments as a format string instance, or we are being handed a fully formatted string.
EDIT: @tobiasgrosser pointed out to me that this patch also fixes a few chipsalliance tests; I added those tests into
builtins.sv. Thanks Tobias!