Bug: op failed to verify that width of result type has to be smaller than or equal to the input type

[dannyoler]

typedef struct packed {
    logic                   element;    
} mystruct_t;

module my_module

#(
    parameter DEPTH = 16              
)
(
    input mystruct_t D_flopped
);

mystruct_t [1:0][DEPTH-1:0] Qall;

always_latch begin
    for ( int array=0 ; array<2 ; array++ ) begin
        for ( int row=0 ; row<DEPTH ; row++ ) begin 
                Qall[array][row] = D_flopped;
        end
    end
end 

endmodule

circt-verilog my_file.sv;

my_file.sv:20:17: error: 'llhd.sig.array_slice' op failed to verify that width of result type has to be smaller than or equal to the input type
                Qall[array][row] = D_flopped;
                ^
my_file.sv:20:17: note: see current operation: %23 = "llhd.sig.array_slice"(%9, %22) : (!llhd.ref<!hw.array<2xarray<16xstruct<element: i1>>>>, i1) -> !llhd.ref<!hw.array<16xstruct<element: i1>>>

This works in all big simulators. I tried forcing casting and bit concatenation but that wouldn't work either. Problem is with the struct. If i replace the struct with just logic type it runs fine.

[fzi-hielscher]

Thanks for the report. This should be fixed now. If there is still a problem feel free to reopen the issue.